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CY14B101LA データシートの表示(PDF) - Cypress Semiconductor

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CY14B101LA
Cypress
Cypress Semiconductor Cypress
CY14B101LA Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
PRELIMINARY
CY14B101LA, CY14B101NA
AC Switching Characteristics
Parameters
Cypress
Alt
Parameters Parameters
Description
20 ns
Min Max
25 ns
Min Max
SRAM Read Cycle
tACE
tACS
tRC[14]
tRC
tAA[15]
tAA
tDOE
tOE
tOHA[15]
tOH
tLZCE[13, 16]
tLZ
tHZCE[13, 16]
tHZ
tLZOE[13, 16]
tOLZ
tHZOE[13, 16]
tOHZ
tPU[13]
tPA
tPD[13]
tPS
tDBE[[13]
-
tLZBE[13]
-
tHZBE[13]
-
SRAM Write Cycle
Chip Enable Access Time
Read Cycle Time
20
25
20
25
Address Access Time
20
25
Output Enable to Data Valid
10
12
Output Hold After Address Change 3
3
Chip Enable to Output Active
3
3
Chip Disable to Output Inactive
8
10
Output Enable to Output Active
0
0
Output Disable to Output Inactive
8
10
Chip Enable to Power Active
0
0
Chip Disable to Power Standby
20
25
Byte Enable to Data Valid
Byte Enable to Output Active
Byte Disable to Output Inactive
10
12
0
0
8
10
tWC
tWC
tPWE
tWP
tSCE
tCW
tSD
tDW
tHD
tDH
tAW
tAW
tSA
tAS
tHA
tWR
tHZWE[13, 16,17] tWZ
tLZWE[13, 16]
tOW
tBW
-
Write Cycle Time
20
25
Write Pulse Width
15
20
Chip Enable To End of Write
15
20
Data Setup to End of Write
8
10
Data Hold After End of Write
0
0
Address Setup to End of Write
15
20
Address Setup to Start of Write
0
0
Address Hold After End of Write
0
0
Write Enable to Output Disable
8
10
Output Active after End of Write
3
3
Byte Enable to End of Write
15
20
Switching Waveforms
Figure 6. SRAM Read Cycle #1: Address Controlled [14, 15, 18]
45 ns
Min Max
45
45
45
20
3
3
15
0
15
0
45
20
0
15
45
30
30
15
0
30
0
0
15
3
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address
Data Output
Previous Data Valid
tOHA
tRC
Address Valid
tAA
Output Data Valid
Notes
14. WE must be HIGH during SRAM read cycles.
15. Device is continuously selected with CE, OE and BHE/BLE LOW.
16. Measured ±200 mV from steady state output voltage.
17. If WE is low when CE goes low, the outputs remain in the high impedance state.
18. HSB must remain HIGH during Read and Write cycles.
Document #: 001-42879 Rev. *C
Page 10 of 24
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