CY14B256KA-SP25XI データシートの表示（PDF） - Cypress Semiconductor

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CY14B256KA-SP25XI

256-Kbit (32 K × 8) nvSRAM with Real Time Clock

Cypress Semiconductor 

CY14B256KA

register clears the alarm flag bit (and all others). A hardware

interrupt pin may also be used to detect an alarm event.

To set, clear or enable an alarm, set the ‘W’ bit (in flags register

– 0x7FF0) to ‘1’ to enable writes to Alarm Registers. After writing

the alarm value, clear the ‘W’ bit back to ‘0’ for the changes to

take effect.

Note CY14B256KA requires the alarm match bit for seconds (bit

‘D7’ in Alarm-Seconds register 0x7FF2) to be set to ‘0’ for proper

operation of Alarm Flag and Interrupt..

Watchdog Timer

The watchdog timer is a free running down counter that uses the

32 Hz clock (31.25 ms) derived from the crystal oscillator. The

oscillator must be running for the watchdog to function. It begins

counting down from the value loaded in the watchdog timer

register.

The timer consists of a loadable register and a free running

counter. On power-up, the watchdog time out value in register

0x7FF7 is loaded into the counter load register. Counting begins

on power-up and restarts from the loadable value any time the

watchdog strobe (WDS) bit is set to ‘1’. The counter is compared

to the terminal value of ‘0’. If the counter reaches this value, it

causes an internal flag and an optional interrupt output. You can

prevent the time out interrupt by setting WDS bit to ‘1’ prior to the

counter reaching ‘0’. This causes the counter to reload with the

watchdog time out value and to be restarted. As long as the user

sets the WDS bit prior to the counter reaching the terminal value,

the interrupt and WDT flag never occur.

New time out values are written by setting the watchdog write bit

to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out

value bits D5–D0 are enabled to modify the time out value. When

WDW is ‘1’, writes to bits D5–D0 are ignored. The WDW function

enables a user to set the WDS bit without concern that the

watchdog timer value is modified. A logical diagram of the

watchdog timer is shown in Figure 3. Note that setting the

watchdog time out value to ‘0’ disables the watchdog function.

The output of the watchdog timer is the flag bit WDF that is set if

the watchdog is allowed to time out. If the watchdog interrupt

enable (WIE) bit in the interrupt register is set, a hardware

interrupt on INT pin is also generated on watchdog timeout. The

flag and the hardware interrupt are both cleared when user reads

the flags register.

.

Figure 3. Watchdog Timer Block Diagram

Oscillator

32,768 KHz

Clock

Divider

32 Hz

Counter

1 Hz

Zero

Compare

WDF

WDS

WDW

DQ

Q

write to

Watchdog

Register

Load

Register

Watchdog

Register

Power Monitor

The CY14B256KA provides a power management scheme with

power fail interrupt capability. It also controls the internal switch

to backup power for the clock and protects the memory from low

VCC access. The power monitor is based on an internal band gap

reference circuit that compares the VCC voltage to VSWITCH

threshold.

As described in the AutoStore Operation on page 4, when

VSWITCH is reached as VCC decays from power loss, a data

STORE operation is initiated from SRAM to the nonvolatile

elements, securing the last SRAM data state. Power is also

switched from VCC to the backup supply (battery or capacitor) to

operate the RTC oscillator.

When operating from the backup source, read and write

operations to nvSRAM are inhibited and the RTC functions are

not available to the user. The RTC clock continues to operate in

the background. The updated RTC time keeping registers data

are available to the user after VCC is restored to the device (see

AutoStore/Power-Up RECALL on page 20).

Interrupts

The CY14B256KA has flags register, interrupt register and

interrupt logic that can signal interrupt to the microcontroller.

There are three potential sources for interrupt: watchdog timer,

power monitor, and alarm timer. Each of these can be individually

enabled to drive the INT pin by appropriate setting in the interrupt

register (0x7FF6). In addition, each has an associated flag bit in

the flags register (0x7FF0) that the host processor uses to

determine the cause of the interrupt. The INT pin driver has two

bits that specify its behavior when an interrupt occurs.

An interrupt is raised only if both a flag is raised by one of the

three sources and the respective interrupt enable bit in interrupts

register is enabled (set to ‘1’). After an interrupt source is active,

two programmable bits, H/L and P/L, determine the behavior of

the output pin driver on INT pin. These two bits are located in the

interrupt register and can be used to drive level or pulse mode

output from the INT pin. In pulse mode, the pulse width is

internally fixed at approximately 200 ms. This mode is intended

to reset a host microcontroller. In the level mode, the pin goes to

its active polarity until the flags register is read by the user. This

mode is used as an interrupt to a host microcontroller. The

control bits are summarized in the following section.

Interrupts are only generated while working on normal power and

are not triggered when system is running in backup power mode.

Note CY14B256KA generates valid interrupts only after the

Powerup RECALL sequence is completed. All events on INT pin

must be ignored for tHRECALL duration after powerup.

Interrupt Register

Watchdog Interrupt Enable (WIE). When set to ‘1’, the

watchdog timer drives the INT pin and an internal flag when a

watchdog time out occurs. When WIE is set to ‘0’, the watchdog

timer only affects the WDF flag in flags register.

Alarm Interrupt Enable (AIE). When set to ‘1’, the alarm match

drives the INT pin and an internal flag. When AIE is set to ‘0’, the

alarm match only affects the AF flag in flags register.

Power Fail Interrupt Enable (PFE). When set to ‘1’, the power

fail monitor drives the pin and an internal flag. When PFE is set

Document Number: 001-55720 Rev. *G

Page 9 of 27

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