CY14B256L(2007) データシートの表示（PDF） - Cypress Semiconductor
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CY14B256L Datasheet PDF : 17 Pages
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PRELIMINARY
CY14B256L
Figure 1. AutoStore Mode
VCAP
VCC
VCC
WE
Hardware STORE (HSB) Operation
The CY14B256L provides the HSB pin for controlling and
acknowledging the STORE operations. Use the HSB pin to
request a hardware STORE cycle. When the HSB pin is driven
low, the CY14B256L conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a WRITE to
the SRAM took place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver that is internally
driven low to indicate a busy condition while the STORE
(initiated by any means) is in progress.
SRAM READ and WRITE operations that are in progress
when HSB is driven low by any means are given time to
complete before the STORE operation is initiated. After HSB
goes low, the CY14B256L continues SRAM operations for
tDELAY. During tDELAY, multiple SRAM READ operations may
take place. If a WRITE is in progress when HSB is pulled low
it will be allowed a time, tDELAY, to complete. However, any
SRAM WRITE cycles requested after HSB goes low will be
inhibited until HSB returns high.
During any STORE operation, regardless of how it was
initiated, the CY14B256L continues to drive the HSB pin low,
releasing it only when the STORE is complete. Upon
completion of the STORE operation the CY14B256L remains
disabled until the HSB pin returns high.
If HSB is not used, it must be left unconnected.
Hardware RECALL (Power Up)
During power up, or after any low power condition
(VCC < VSWITCH), an internal RECALL request will be latched.
When VCC once again exceeds the sense voltage of VSWITCH,
a RECALL cycle will automatically be initiated and takes
tHRECALL to complete.
Software STORE
Data can be transferred from the SRAM to the nonvolatile
memory by a software address sequence. The CY14B256L
software STORE cycle is initiated by executing sequential
CE-controlled READ cycles from six specific address locations
in exact order. During the STORE cycle an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. Once a STORE cycle is
initiated, further input and output are disabled until the cycle is
completed.
Because a sequence of READs from specific addresses is
used for STORE initiation, it is important that no other READ
or WRITE accesses intervene in the sequence, or the
sequence will be aborted and no STORE or RECALL takes
place.
To initiate the software STORE cycle, the following READ
sequence must be performed:
1. Read address 0x0E38, valid READ
2. Read address 0x31C7, valid READ
3. Read address 0x03E0, valid READ
4. Read address 0x3C1F, valid READ
5. Read address 0x303F, valid READ
6. Read address 0x0FC0, initiate STORE cycle
The software sequence may be clocked with CE-controlled
READs or OE-controlled READs. Once the sixth address in
the sequence has been entered, the STORE cycle
commences, and the chip will be disabled. It is important that
READ cycles and not WRITE cycles be used in the sequence.
It is not necessary that OE be low for the sequence to be valid.
After the tSTORE cycle time has been fulfilled, the SRAM will
again be activated for READ and WRITE operation.
Software RECALL
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL
cycle is initiated with a sequence of READ operations in a
manner similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of CE-controlled
READ operations must be performed:
1. Read address 0x0E38, valid READ
2. Read address 0x31C7, valid READ
3. Read address 0x03E0, valid READ
4. Read address 0x3C1F, valid READ
5. Read address 0x303F, valid READ
6. Read address 0x0C63, initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is
transferred into the SRAM cells. After the tRECALL cycle time
the SRAM will once again be ready for READ and WRITE
operations. The RECALL operation does not alter the data in
the nonvolatile elements.
Data Protection
The CY14B256L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when VCC < VSWITCH. If the CY14B256L is in a WRITE mode
(both CE and WE low) at power up, after a RECALL, or after
a STORE, the WRITE will be inhibited until a negative
transition on CE or WE is detected. This protects against
inadvertent writes during power up or brownout conditions.
Document #: 001-06422 Rev. *E
Page 4 of 17
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