CY14B256L データシートの表示（PDF） - Cypress Semiconductor
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CY14B256L Datasheet PDF : 18 Pages
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CY14B256L
AC Switching Characteristics
SRAM Read Cycle
Parameter
Cypress
Parameter
Alt
Description
25 ns
Min Max
35 ns
Min Max
tACE
tRC [6]
tAA [7]
tDOE
tOHA [7]
tLZCE [8]
tHZCE [8]
tLZOE [8]
tHZOE [8]
tPU [5]
tPD [5]
tELQV
tAVAV, tELEH
tAVQV
tGLQV
tAXQX
tELQX
tEHQZ
tGLQX
tGHQZ
tELICCH
tEHICCL
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
25
35
25
35
25
35
12
15
3
3
3
3
10
13
0
0
10
13
0
0
25
35
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled [6, 7, 9]
45 ns
Unit
Min Max
45 ns
45
ns
45 ns
20 ns
3
ns
3
ns
15 ns
0
ns
15 ns
0
ns
45 ns
W5&
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Figure 6. SRAM Read Cycle 2: CE Controlled [6, 9]
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2(
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W5&
W/=&(
W$&(
W'2(
W/=2(
W3'
W+=&(
W+=2(
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W38
,&&
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Notes
6. WE must be HIGH during SRAM Read cycles.
7. Device is continuously selected with CE and OE both Low.
8. Measured ±200 mV from steady state output voltage.
9. HSB must remain HIGH during SRAM Read and Write Cycles.
Document Number: 001-06422 Rev. *H
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Page 9 of 18
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