CY2213 データシートの表示（PDF） - Cypress Semiconductor

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CY2213

High-Frequency Programmable PECL Clock Generator

Cypress Semiconductor 

CY2213

S data

S clk

S clk_ C

Rp

Sdata_ C

Rp

VDD

S data_ C

S clk_ in

S data_ in

S clk_ in

Sdata_ in

M aster D evice

Slave Device

Figure 1. Device Connections

Sclk

Sdata

Start (S)

valid data

Acknowledge

FigFuirge. 22. SSeerriiaall IInntteerrffaaccee SSppeecciifficicaattioionnss

Stop (P)

1 bit

7 bits

1 bit 1 bit

S Slave Address R/W Ack

8 bits

1 bit

8 bits

1 bit 8 bits

Dummy Byte 0 Ack Dummy Byte 1 Ack Data 0

1 bit

Ack

Data 1

8 bits

Ack P

1 bit

Figure 3. CY2213 Transfer Format

Serial Interface Address for the CY2213

A6

A5

A4

A3

A2

1

1

0

0

1

Serial Interface Programming for the CY2213

Data0

Data1

Data2

b7

QCNTBYP

P<7>

Reserved

b6

SELPQ

P<6>

Reserved

b5

Q<5>

P<5>

Reserved

b4

Q<4>

P<4>

Reserved

b3

Q<3>

P<3>

Reserved

A1

0

b2

Q<2>

P<2>

Reserved

A0

1

b1

Q<1>

P<1>

Reserved

R/W

0

b0

Q<0>

P<0>

Reserved

To program the CY2213 using the two-wire serial interface, set

the SELPQ bit HIGH. The default setting of this bit is LOW. The

P and Q values are determined by the following formulas:

Pfinal = (P7..0 + 3) * 2

Qfinal = Q5..0 + 2.

If the QCNTBYP bit is set HIGH, then Qfinal defaults to a value

of 1. The default setting of this bit is LOW.

If the SELPQ bit is set LOW, the PLL multipliers will be set

using the values in the Select Function Table.

CyberClocks™ has been developed to generate P and Q

values for stable PLL operation. This software is downloadable

from www.cypress.com.

Document #: 38-07263 Rev. *E

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