CY2213 データシートの表示（PDF） - Cypress Semiconductor

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CY2213

High-Frequency Programmable PECL Clock Generator

Cypress Semiconductor 

CY2213

The PECL differential driver is designed for low-voltage,

high-frequency operation. It significantly reduces the transient

switching noise and power dissipation when compared to

conventional CMOS drivers. The nominal value of the channel

impedance is 50Ω. The pull-up and pull-down resistors provide

matching channel termination. The combination of the differ-

ential driver and the output network determines the voltage

swing on the channel. The output clock is specified at the

measurement point indicated in Figure 5 and Figure 6.

Signal Waveforms

Input and Output voltage waveforms are defined as shown in

Figure 8. Rise and fall times are defined as the 20% and 80%

measurement points of VOHmin – VOLmax.

The device parameters are defined in Table 1. Figure 9 shows

the definition of long-term duty cycle, which is simply the CLK

waveform high-time divided by the cycle time (defined at the

crossing point). Long-term duty cycle is the average over

many (> 10,000) cycles. DC is defined as the output clock

long-term duty cycle.

A physical signal that appears at the pins of the device is

deemed valid or invalid depending on its voltage and timing

relations with other signals. This section defines the voltage

and timing waveforms for the input and output pins of the

CY2213. The Device Characteristics tables list the specifica-

tions for the device parameters that are defined here.

Table 1. Definition of Device Parameters

Parameter

Definition

VOH, VOL

VIH, VIL

tCR, tCF

Clock output high and low voltages

VDD LVCMOS input high and low voltages

Clock output rise and fall times

V(t)

CLK

tCF

tCR

Figure 8. Voltage Waveforms

VOHmin

80%

20%

VOLmax

CLKB

tPW+

tCYCLE

DC = tPW+/tCYCLE

Figure 9. Duty CycleJitter

Jitter

This section defines the specifications that relate to timing

uncertainty (or jitter) of the input and output waveforms.

Figure 10 shows the definition of period jitter with respect to

the falling edge of the CLK signal. Period jitter is the difference

between the minimum and maximum cycle times over many

cycles (typically 12800 cycles at 400 MHz). Equal require-

ments apply for rising edges of the CLK signal. tJP is defined

as the output period jitter.

Figure 11 shows the definition of cycle-to-cycle jitter with

respect to the falling edge of the CLK signal. Cycle-to-cycle

jitter is the difference between cycle times of adjacent cycles

over many cycles (typically 12800 cycles at 400 MHz). Equal

requirements apply for rising edges of the CLK signal. tJC is

defined as the clock output cycle-to-cycle jitter.

Document #: 38-07263 Rev. *E

Page 7 of 10

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