CY22150ZI データシートの表示（PDF） - Cypress Semiconductor

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CY22150ZI

One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator

Cypress Semiconductor 

CY22150

Part Number Outputs

Input Frequency Range

CY22150FC

6 8 MHz–30 MHz (external crystal)

1 MHz–133 MHz (driven clock)

CY22150FI

6 8 MHz–30 MHz (external crystal)

1 MHz–133 MHz (driven clock)

Output Frequency Range

80 kHz–200 MHz (3.3V)

80 KHz–166.6 MHz (2.5V)

80 kHz – 166.6 MHz (3.3V)

80 KHz – 150 MHz (2.5V)

Specifications

Field programmable

Serially programmable

Commercial temperature

Field programmable

Serially programmable

Industrial temperature

Pin Definitions

Pin Name

XIN

VDD

AVDD

SDAT

AVSS

VSSL

LCLK1

LCLK2

LCLK3

SCLK

VDDL

LCLK4

VSS

CLK5

CLK6

XOUT[1]

Pin Number

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Pin Description

Reference Input. Driven by a crystal (8 MHz – 30 MHz) or external clock (1 MHz – 133 MHz).

Programmable input load capacitors allow for maximum flexibility in selecting a crystal,

regardless of manufacturer, process, performance, or quality.

3.3V voltage supply

3.3V analog voltage supply

Serial data input

Analog ground

LCLK ground

Configurable clock output 1 at VDDL level (3.3V or 2.5V)

Configurable clock output 2 at VDDL level (3.3V or 2.5V)

Configurable clock output 3 at VDDL level (3.3V or 2.5V)

Serial clock input

LCLK voltage supply (2.5V or 3.3V)

Configurable clock output 4 at VDDL level (3.3V or 2.5V)

Ground

Configurable clock output 5 (3.3V)

Configurable clock output 6 (3.3V)

Reference output

Frequency Calculation and Register Definitions

The CY22150 is an extremely flexible clock generator with four

basic variables that can be used to determine the final output

frequency. They are the input reference frequency (REF), the

internally calculated P and Q dividers, and the post divider,

which can be a fixed or calculated value. There are three basic

formulas for determining the final output frequency of a

CY22150-based design:

• CLK = ((REF * P)/Q)/Post Divider

• CLK = REF/Post Divider

• CLK = REF.

Note:

1. Float XOUT if XIN is driven by an external clock source.

The basic PLL block diagram is shown in Figure 1. Each of the

six clock outputs on the CY22150 has a total of seven output

options available to it. There are six post divider options

available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N

and DIV2N are independently calculated and are applied to

individual output groups. The post divider options can be

applied to the calculated VCO frequency ((REF*P)/Q) or to the

REF directly.

In addition to the six post divider output options, the seventh

option bypasses the PLL and passes the REF directly to the

crosspoint switch matrix.

Document #: 38-07104 Rev. *F

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