CY62256VNLL(2011) データシートの表示（PDF） - Cypress Semiconductor

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CY62256VNLL
(Rev.:2011)

256K (32K × 8) Static RAM

Cypress Semiconductor 

CY62256VN

Switching Waveforms

Figure 3. Read Cycle No. 1[14, 15]

ADDRESS

DATA OUT

CE

tRC

tAA

tOHA

PREVIOUS DATA VALID

Figure 4. Read Cycle No. 2[15, 16]

t RC

OE

DATA OUT

VCC

SUPPLY

CURRENT

tACE

tDOE

t LZOE

HIGH IMPEDANCE

tLZCE

t PU

50%

DATA VALID

DATA VALID

t HZOE

tHZCE

HIGH

IMPEDANCE

t PD

ICC

50%

ISB

ADDRESS

Figure 5. Write Cycle No. 1 (WE Controlled)[17, 18, 19]

tWC

CE

tAW

tHA

tSA

WE

t PWE

OE

DATA I/O

NOTE 20

t HZOE

tSD

tHD

DATAINVALID

Notes

14. Device is continuously selected. OE, CE = VIL.

15. WE is HIGH for read cycle.

16. Address valid prior to or coincident with CE transition LOW.

17. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can

terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

18. Data I/O is high impedance if OE = VIH.

19. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.

20. During this period, the I/Os are in output state and input signals should not be applied.

Document Number: 001-06512 Rev. *D

Page 7 of 14

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