CY7B9910-2SC PDF VIEW DOWNLOAD, CY7B9910-2SC データシート

CY7B9910-2SC(1997) データシートの表示（PDF） - Cypress Semiconductor

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CY7B9910-2SC
(Rev.:1997)

Cypress Semiconductor

CY7B9910-2SC Datasheet PDF : 7 Pages

1 2 3 4 5 6 7

CY7B9910

CY7B9920

SYSTEM

CLOCK

REF

TEST

REF

LOAD

7B9910–9

Figure 1. Zero-Skew and/or Zero-Delay Clock Driver

Operational Mode Descriptions

Figure 1 shows the device configured as a zero-skew clock

buffer. In this mode the 7B9910/9920 can be used as the basis

for a low-skew clock distribution tree. The outputs are aligned

and may each drive a terminated transmission line to an inde-

pendent load. The FB input can be tied to any output and the

operating frequency range is selected with the FS pin. The

low-skew specification, coupled with the ability to drive termi-

nated transmission lines (with impedances as low as 50

ohms), allows efficient printed circuit board design.

Figure 2 shows the CY7B9910/9920 connected in series to

construct a zero-skew clock distribution tree between boards.

Cascaded clock buffers will accumulate low-frequency jitter

because of the non-ideal filtering characteristics of the PLL

filter. It is not recommended that more than two clock buffers

be connected in series.

SYSTEM

CLOCK

REF

TEST

LOAD

REF

TEST

LOAD

7B9910–10

Figure 2. Board-to-Board Clock Distribution

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