CY7B9945V-5AC(2003) データシートの表示（PDF） - Cypress Semiconductor

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CY7B9945V-5AC
(Rev.:2003)

High-speed Multi-phase PLL Clock Buffer

Cypress Semiconductor 

RoboClock

CY7B9945V

AC Test Loads and Waveforms[23]

3.3V

R1

For LOCK output only For all other outputs

OUTPUT

R1 = 910 Ω

R2 = 910 Ω

R1 = 100Ω

R2 = 100Ω

CL

CL < 30 pF

CL < 25 pF to 185 MHz

R2

or 10 pF at 200 MHz

(Includes fixture and

probe capacitance)

3.3V

GND

< 1 ns

(a) LVTTL AC Test Load

2.0V

0.8V

2.0V

0.8V

< 1 ns

(b) TTL Input Test Waveform

AC Timing Diagram

REF

tPD

FB

Q

tREFpwh

tREFpwl

tPWH

2.0V

tPWL

0.8V

tCCJ1-3,4-12

REF TO DEVICE 1 and 2

tPD

FB DEVICE1

tPDELTA

FB DEVICE2

tPDELTA

tSKEWPR

tSKEWPR

[1:2]Q[0,2]

[1:2]Q[1,3]

[1:2]Q[0:3]

tSKEWBNK

[1:2]Q[0:3]

tSKEWBNK

Q

tSKEW0,1

Other Q

tODCV

tODCV

tSKEW0,1

Notes:

20. UI = unit interval. Examples: 1 UI is a full period. 0.1UI is 10% of period.

21. Measured at 0.5V deviation from starting voltage.

22. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 185 MHz or 10 pF to 200 MHz.

23. These figures are for illustration purposes only. The actual ATE loads may vary.

Document #: 38-07336 Rev. *D

Page 8 of 10

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