CY7B9945V-2AXI(2011) データシートの表示（PDF） - Cypress Semiconductor

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CY7B9945V-2AXI
(Rev.:2011)

High Speed Multi-phase PLL Clock Buffer

Cypress Semiconductor 

PRELIMINARY

RoboClock®

CY7B9945V

REF

tPD

FB

Q

Figure 4. AC Test Loads and Waveforms

For LOCK output only For all other outputs

R1 = 910 Ω

R2 = 910 Ω

R1 = 100Ω

R2 = 100Ω

CL < 30 pF

CL < 25 pF to 185 MHz

(Includes fixture and or 10 pF at 200 MHz

probe capacitance)

OUTPUT

CL

3.3 V

R1

R2

3.3 V

(a) LVTTL AC Test Load

2.0 V

2.0 V

GND

0.8 V

0.8 V

< 1 ns

< 1 ns

(b) TTL Input Test Waveform

Figure 5. AC Timing Diagram

tREFpwh

tREFpwl

tPWH

2.0 V

tPWL

0.8 V

tCCJ1-3,4-12

tSKEWPR

tSKEWPR

[1:2]Q[0:3]

tSKEWBNK

tSKEWBNK

REF TO DEVICE 1 and 2

tPD

FB DEVICE1

tPDELTA

FB DEVICE2

tPDELTA

[1:2]Q[0:3]

Q

tSKEW0,1

Other Q

tODCV

tODCV

tSKEW0,1

[1:2]Q[0,2]

[1:2]Q[1,3]

.

Notes

14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affects these parameters.

15. Rise and fall times are measured between 2.0 V and 0.8 V.

16. fNOM must be within the frequency range defined by the same FS state.

17. tPWH is measured at 2.0 V. tPWL is measured at 0.8 V.

18. UI = unit interval. Examples: 1 UI is a full period. 0.1UI is 10% of period.

19. Measured at 0.5 V deviation from starting voltage.

20. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 185 MHz or 10 pF to 200 MHz

21. These figures are for illustration purposes only. The actual ATE loads may vary.

Document Number: 38-07336 Rev. *J

Page 10 of 15

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