CY7B9945V-2AXI(2011) データシートの表示（PDF） - Cypress Semiconductor
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CY7B9945V-2AXI Datasheet PDF : 15 Pages
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PRELIMINARY
RoboClock®
CY7B9945V
Pinouts
Figure 1. Pin Configuration
2F1
2F0
2DS1
GND
2Q0
VCCN
2Q1
2Q2
VCCN
2Q3
GND
1DS1
2DS0
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
3
37
4
36
5
35
6
7
CY7B9945V
34
33
8
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
REFA-
REFSEL
REFB-
REFB+
1F2
FS
GND
1Q2
VCCN
1Q3
FBF0
1F0
VCCQ
Pin Definitions
Pin
34
40,39, 36,37
38
Name
FS
IO
Input
REFA+,
REFA-
REFB+,
REFB-
REFSEL
Input
Input
42
FBK
Input
28,18, 35,17, 2, 1 1F[0:3],
2F[0:1]
19,26
DIS[1:2]
Input
Input
14,12, 13,3
29
[1:2]DS[0:
1]
FBF0
Input
Input
50,51
FBDS[0:1] Input
48,46, 32,30, 1Q[0:3], Output
5,7,8,10, 20,22 2Q[0:5]
44
QF
Output
52
LOCK
Output
Type
Description
Three level Frequency Select. This input must be set according to the nominal frequency
Input (fNOM). See Table 1.
LVTTL/ Reference Inputs. These inputs can operate as differential PECL or
LVDIFF single-ended TTL reference inputs to the PLL. When operating as a
single-ended LVTTL input, the complementary input is left open.
LVTTL
Reference Select Input. The REFSEL input controls the configuration of
reference input When LOW, it uses the REFA pair as the reference input. When
HIGH, it uses the REFB pair as the reference input. This input has an internal
pull down.
LVTTL
Feedback Input Clock. The PLL operates such that the rising edges of the
reference and feedback signals are aligned in phase and frequency. This pin
provides the clock output QF feedback to the phase detector.
Three level Output Phase Function Select. Each pair determines the phase of the
Input respective bank of outputs. See Table 3.
LVTTL
Output Disable. Each input controls the state of the respective output bank.
When HIGH, the output bank is disabled to HOLD-OFF or High-Z state; the
disable state is determined by MODE. When LOW, outputs 1Q[0:3] and 2Q[0:5]
are enabled. See Table 5.
Three level Output Divider Function Select. Each pair determines the divider ratio of the
Input respective bank of outputs. See Table 4.
Three level Feedback Output Phase Function Select. This input determines the phase
Input of the QF output. See Table 3.
Three level Feedback Output Divider Function Select. This input determines the divider
Input ratio of the QF output. See Table 4.
LVTTL
Clock Outputs with Adjustable Phases and fNOM Divide Ratios. The output
frequencies and phases are determined by [1:2]DS[0:1], and 1F[0:3] and
2F[0:1], respectively. See Table 3 and Table 4.
LVTTL
Feedback Clock Output. This output is connected to the FBK input. The output
frequency and phase are determined by FBDS[0:1] and FBF0, respectively.
See Table 3 and Table 4.
LVTTL
PLL Lock Indicator. When HIGH, this output indicates that the internal PLL is
locked to the reference signal. When LOW, it indicates that the PLL is
attempting to acquire lock
Document Number: 38-07336 Rev. *J
Page 3 of 15
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