CY7B9945V-2AXI(2011) データシートの表示（PDF） - Cypress Semiconductor
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CY7B9945V-2AXI Datasheet PDF : 15 Pages
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PRELIMINARY
RoboClock®
CY7B9945V
Pin Definitions
Pin
25
Name
MODE
6,9,21, 31, 45, 47 VCCN
16,27, 41
VCCQ
4,11,15, 23,24, GND
33,43,49
IO
Input
Type
Description
Three level This pin determines the clock outputs’ disable state. When this input is
Input HIGH, the clock outputs disables to high impedance state (High-Z). When this
input is LOW, the clock outputs disables to HOLD-OFF mode. When in MID,
the device enters factory test mode.
PWR Power Supply for the Output Buffers
PWR Power Supply for the Internal Circuitry
PWR Device Ground
Block Diagram Description
Divide and Phase Select Matrix
The PLL adjusts the phase and the frequency of its output signal
to minimize the delay between the reference (REFA/B+,
REFA/B-) and the feedback (FB) input signals.
The CY7B9945V has a flexible REF input scheme. These inputs
enable the use of either differential LVPECL or single ended
LVTTL inputs. To configure as single ended LVTTL inputs, leave
the complementary pin open (internally pulled to 1.5 V), then the
other input pin is used as a LVTTL input. The REF inputs are also
tolerant to hot insertion.
The REF inputs are changed dynamically. When changing from
one reference input to the other reference input of the same
frequency, the PLL is optimized to ensure that the clock outputs
period is not less than the calculated system budget (tMIN =
tREF (nominal reference period) – tCCJ (cycle-cycle jitter) –
tPDEV (max. period deviation)) while reacquiring lock.
The FS control pin setting determines the nominal operational
frequency range of the divide by one output (fNOM) of the
device. fNOM is directly related to the VCO frequency. The FS
setting for the device is shown in Table 1. For CY7B9945V, the
upper fNOM range extends from 96 MHz to 200 MHz.
Table 1. Frequency Range Select
FS[1]
LOW
MID
HIGH
fNOM (MHz)
Min
Max
24
52
48
100
96
200
Time Unit Definition
Selectable skew is in discrete increments of time unit (tU). The
value of a tU is determined by the FS setting and the maximum
nominal output frequency. The equation determines the tU value
as follows:
tU = 1/(fNOM*N).
N is a multiplication factor that is determined by the FS setting.
fNOM is nominal frequency of the device. N is defined in Table 2.
Table 2. N Factor Determination
FS
LOW
MID
HIGH
CY7B9945V
N
fNOM (MHz) at which tU = 1.0 ns
32
31.25
16
62.5
8
125
The Divide Select Matrix is comprised of three independent
banks: two of clock outputs and one for feedback. The Phase
Select Matrix, enables independent phase adjustments on
1Q[0:1], 1Q[2:3] and 2Q[0:5]. The frequency of 1Q[0:3] is
controlled by 1DS[0:1] while the frequency of 2Q[0:5] is
controlled by 2DS[0:1]. The phase of 1Q[0:1] is controlled by
1F[0:1], that of 1Q[2:3] is controlled by 1F[2:3] and that of 2Q[0:5]
is controlled by 2F[0:1].
The high fanout feedback output buffer (QF) connects to the
feedback input (FBK).This feedback output has one phase
function select input (FBF0) and two divider function selects
FBDS[0:1].
The phase capabilities that are chosen by the phase function
select pins are shown in Table 3. The divide capabilities for each
bank are shown in Table 4.
Table 3. Output Phase Select
Control Signal
1F1
1F0
1F3
1F2
Output Phase Function
1Q[0:1]
1Q[2:3]
2F1
LOW
LOW
LOW
MID
MID
MID
HIGH
HIGH
HIGH
2F0
FBF0
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
–4tU
–3tU
–2tU
–1tU
0tU
+1tU
+2tU
+3tU
+4tU
–4tU
–3tU
–2tU
–1tU
0tU
+1tU
+2tU
+3tU
+4tU
2Q[0:5]
–8tU
–7tU
–6tU
BK1Q[0:1][2]
0tU
BK1Q[2:3][2]
+6tU
+7tU
+8tU
QF
–4tU
N/A
N/A
N/A
0tU
N/A
N/A
N/A
+4tU
Table 4. Output Divider Select
Control Signal
[1:2]DS1 [1:2]DS0
and FBDS1 and
FBDS0
LOW
LOW
LOW
MID
LOW
HIGH
Output Divider Function
Bank1 Bank2 Feedback
/1
/1
/1
/2
/2
/2
/3
/3
/3
Document Number: 38-07336 Rev. *J
Page 4 of 15
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