CY7B9945V-2AXCT(2011) データシートの表示（PDF） - Cypress Semiconductor
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CY7B9945V-2AXCT Datasheet PDF : 15 Pages
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PRELIMINARY
RoboClock®
CY7B9945V
Table 4. Output Divider Select
Control Signal
[1:2]DS1 [1:2]DS0
and FBDS1 and
FBDS0
MID
LOW
MID
MID
MID
HIGH
HIGH
LOW
HIGH
MID
HIGH
HIGH
Output Divider Function
Bank1 Bank2 Feedback
/4
/4
/4
/5
/5
/5
/6
/6
/6
/8
/8
/8
/ 10
/ 10
/ 10
/ 12
/ 12
/ 12
Figure 2 shows the timing relationship of programmable skew
outputs. All times are measured with respect to REF with the
output used for feedback programmed with 0tU skew. The PLL
naturally aligns the rising edge of the FB input and REF input. If
the output used for feedback is programmed to another skew
position, then the whole tU matrix shifts with respect to REF. For
example, if the output used for feedback is programmed to shift
–4tU, then the whole matrix is shifted forward in time by 4tU.
Thus an output programmed with 4tU of skew gets effectively be
skewed 8tU with respect to REF.
Figure 2. Typical Outputs with FB Connected to a Zero-Skew Output[3]
1F[1:0]
1F[3:2]
(N/A)
(N/A)
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
FBInput
REFInput
2F[1:0]
LL
LM
LH
(N/A)
(N/A)
(N/A)
(N/A)
MM
(N/A)
(N/A)
(N/A)
(N/A)
HL
HM
HH
–8tU
–7tU
–6tU
–4tU
–3tU
–2tU
–1tU
0t U
+1t U
+2t U
+3t U
+4t U
+6t U
+7t U
+8t U
Document Number: 38-07336 Rev. *J
Page 5 of 15
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