CY7B9945V-2AXI データシートの表示（PDF） - Cypress Semiconductor

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CY7B9945V-2AXI

High Speed Multi-phase PLL Clock Buffer

Cypress Semiconductor 

PRELIMINARY

RoboClock®

CY7B9945V

High Speed Multi-phase PLL Clock Buffer

Features

■ 500 ps max Total Timing Budget™ (TTB™) window

■ 24–200 MHz input and output operation

■ Low output-output skew < 200 ps

■ 10 + 1 LVTTL outputs driving 50W terminated lines

■ Dedicated feedback output

■ Phase adjustments in 625/1300 ps steps up to +10.4 ns

■ 3.3V LVTTL/LVPECL, fault tolerant, and hot insertable

reference inputs

■ Multiply or divide ratios of 1–6, 8, 10, and 12

■ Individual output bank disable

■ Output high impedance option for testing purposes

■ Integrated phase locked loop (PLL) with lock indicator

■ Low cycle-cycle jitter (<100 ps peak-peak)

■ 3.3V operation

■ Industrial temperature range: –40°C to +85°C

■ 52-pin 1.4 mm TQFP package

Functional Description

The CY7B9945V high speed multi-phase PLL clock buffer offers

user selectable control over system clock functions. This multiple

output clock driver provides the system integrator with functions

necessary to optimize the timing of high performance computer

and communication systems.

The device features a guaranteed maximum TTB window speci-

fying all occurrences of output clocks. This includes the input

reference clock across variations in output frequency, supply

voltage, operating temperature, input edge rate, and process.

Ten configurable outputs each drive terminated transmission

lines with impedances as low as 50W while delivering minimal

and specified output skews at LVTTL levels. The outputs are

arranged in two banks of four and six outputs. These banks

enable a divide function of 1 to 12, with phase adjustments in 625

ps–1300 ps increments up to ±10.4 ns. The dedicated feedback

output enables divide-by functionality from 1 to 12 and limited

phase adjustments. However, if needed, any one of the ten

outputs can be connected to the feedback input as well as driving

other inputs.

Selectable reference input is a fault tolerant feature that enables

smooth change over to a secondary clock source when the

primary clock source is not in operation. The reference inputs

and feedback inputs are configurable to accommodate both

LVTTL or Differential (LVPECL) inputs. The completely

integrated PLL reduces jitter and simplifies board layout.

Logic Block Diagram

FS

3

REFA+

REFA-

REFB+

REFB-

REFSEL

FBK

MODE

PLL

FBF0

3

FBDS0

3

FBDS1

3

1F0

3

1F1

3

1D S 0

3

1D S 1

3

1F2

3

1F3

3

2F0

3

2F1

3

2DS0

3

2D S 1

3

LO C K

D iv id e

and

Phase

S e le c t

D iv id e

and

Phase

S e le c t

D IS 1

D iv id e

and

Phase

S e le c t

D IS 2

QF

1Q 0

1Q 1

1Q 2

1Q 3

2Q 0

2Q 1

2Q 2

2Q 3

2Q 4

2Q 5

Cypress Semiconductor Corporation • 198 Champion Court

Document Number: 38-07336 Rev. *F

• San Jose, CA 95134-1709 • 408-943-2600

Revised June 21, 2007

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