CY7B9945V-5AXCT データシートの表示（PDF） - Cypress Semiconductor

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CY7B9945V-5AXCT

High Speed Multi-phase PLL Clock Buffer

Cypress Semiconductor 

PRELIMINARY

CY7B9945V

Pin Definitions

Pin

Name

34

FS

40,39, REFA+, REFA-

36,37 REFB+, REFB-

38

REFSEL

42

FBK

28,18, 1F[0:3], 2F[0:1]

35,17, 2,

1

19,26 DIS[1:2]

14,12,

13,3

29

[1:2]DS[0:1]

FBF0

50,51 FBDS[0:1]

48,46, 1Q[0:3], 2Q[0:5]

32,30,

5,7,8,10

, 20,22

44

QF

52

LOCK

25

MODE

6,9,21, VCCN

31, 45,

47

16,27, VCCQ

41

4,11,15, GND

23,24,

33,43,4

9

IO

Input

Input

Input

Input

Input

Type

Description

Three level

Input

LVTTL/

LVDIFF

Frequency Select. This input must be set according to the nominal frequency

(fNOM). See Table 1.

Reference Inputs. These inputs can operate as differential PECL or

single-ended TTL reference inputs to the PLL. When operating as a

single-ended LVTTL input, the complementary input is left open.

LVTTL

Reference Select Input. The REFSEL input controls the configuration of

reference input When LOW, it uses the REFA pair as the reference input. When

HIGH, it uses the REFB pair as the reference input. This input has an internal

pull down.

LVTTL

Feedback Input Clock. The PLL operates such that the rising edges of the

reference and feedback signals are aligned in phase and frequency. This pin

provides the clock output QF feedback to the phase detector.

Three level Output Phase Function Select. Each pair determines the phase of the

Input respective bank of outputs. See Table 3.

Input

Input

Input

Input

Output

LVTTL

Output Disable. Each input controls the state of the respective output bank.

When HIGH, the output bank is disabled to HOLD-OFF or High-Z state; the

disable state is determined by MODE. When LOW, outputs 1Q[0:3] and 2Q[0:5]

are enabled. See Table 5.

Three level Output Divider Function Select. Each pair determines the divider ratio of the

Input respective bank of outputs. See Table 4.

Three level Feedback Output Phase Function Select. This input determines the phase of

Input the QF output. See Table 3.

Three level Feedback Output Divider Function Select. This input determines the divider

Input ratio of the QF output. See Table 4.

LVTTL

Clock Outputs with Adjustable Phases and fNOM Divide Ratios. The output

frequencies and phases are determined by [1:2]DS[0:1], and 1F[0:3] and

2F[0:1], respectively. See Table 3 and Table 4.

Output

Output

Input

LVTTL

Feedback Clock Output. This output is connected to the FBK input. The output

frequency and phase are determined by FBDS[0:1] and FBF0, respectively. See

Table 3 and Table 4.

LVTTL

PLL Lock Indicator. When HIGH, this output indicates that the internal PLL is

locked to the reference signal. When LOW, it indicates that the PLL is attempting

to acquire lock

Three level This pin determines the clock outputs’ disable state. When this input is

Input HIGH, the clock outputs disables to high impedance state (High-Z). When this

input is LOW, the clock outputs disables to HOLD-OFF mode. When in MID, the

device enters factory test mode.

PWR Power Supply for the Output Buffers

PWR Power Supply for the Internal Circuitry

PWR Device Ground

Document Number: 38-07336 Rev. *F

Page 3 of 11

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