CY7B9945V-5AXCT データシートの表示（PDF） - Cypress Semiconductor

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CY7B9945V-5AXCT

High Speed Multi-phase PLL Clock Buffer

Cypress Semiconductor 

PRELIMINARY

CY7B9945V

Lock Detect Output Description

The LOCK detect output indicates the lock condition of the

integrated PLL. Lock detection is accomplished by comparing

the phase difference between the reference and feedback

inputs. Phase error is declared when the phase difference

between the two inputs is greater than the specified device

propagation delay limit tPD.

When in the locked state, after four or more consecutive

feedback clock cycles with phase errors, the LOCK output is

forced LOW to indicate out-of-lock state.

When in the out-of-lock state, 32 consecutive phase errorless

feedback clock cycles are required to enable the LOCK output to

indicate lock condition (LOCK = HIGH).

If the feedback clock is removed after LOCK has gone HIGH, a

“Watchdog” circuit is implemented to indicate the out-of-lock

condition after a time-out period by deasserting LOCK LOW. This

time out period is based upon a divided down reference clock.

This assumes that there is activity on the selected REF input. If

there is no activity on the selected REF input then the LOCK

detect pin does not accurately reflect the state of the internal

PLL.

Factory Test Mode Description

The device enters factory test mode when the MODE is driven

to MID. In factory test mode, the device operates with its internal

PLL disconnected; input level supplied to the reference input is

used in place of the PLL output. In TEST mode the FB input is

tied LOW. All functions of the device remain operational in

factory test mode except the internal PLL and output bank

disables. The MODE input is designed as a static input. Dynam-

ically toggling this input from LOW to HIGH temporarily causes

the device to go into factory test mode (when passing through

the MID state).

When in the test mode, the device is reset to a deterministic state

by driving the DIS2 input HIGH. Doing so disables all outputs

and, after the selected reference clock pin has five positive

transitions, all internal finite state machines (FSM) are set at a

deterministic state. The states depend on the configurations of

the divide, skew and frequency selection. All clock outputs stay

in High-Z mode and all FSMs stay in the deterministic state until

DIS2 is deasserted. This causes the device to reenter factory

test mode.

Safe Operating Zone

Figure 2 shows the operating condition of the device not

exceeding its allowable maximum junction temperature of

150°C. Figure 2 shows the maximum number of outputs that can

operate at 185 MHz (with 25 pF load and no air flow) or 200 MHz

(with 10-pF load and no air flow) at various ambient tempera-

tures. At the limit line, all other outputs are configured to

divide-by-two (i.e., operating at 92.5 MHz) or lower frequencies.

The device operates below maximum allowable junction temper-

ature of 150°C when its configuration (with the specified

constraints) falls within the shaded region (safe operating zone).

Figure 2 shows that at 85°C, the maximum number of outputs

that can operate at 200 MHz is 6.

Figure 2. Typical Safe Operating Zone

Typical Safe Operating Zone

(25-pF Load, 0-m/s air flow)

100

95

90

85

80

75

70

Safe Operating Zone

65

60

55

50

2

4

6

8

10

Number of Outputs at 185 MHz

Document Number: 38-07336 Rev. *F

Page 6 of 11

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