CY7B9945V-5AXCT データシートの表示（PDF） - Cypress Semiconductor
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CY7B9945V-5AXCT Datasheet PDF : 11 Pages
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PRELIMINARY
CY7B9945V
AC Test Loads and Waveform
Figure 3. AC Test Loads and Waveforms [22]
For LOCK output only For all other outputs
R1 = 910 Ω
R2 = 910 Ω
R1 = 100Ω
R2 = 100Ω
CL < 30 pF
CL < 25 pF to 185 MHz
(Includes fixture and or 10 pF at 200 MHz
probe capacitance)
OUTPUT
CL
3.3V
R1
R2
3.3V
(a) LVTTL AC Test Load
2.0V
2.0V
GND
0.8V
0.8V
< 1 ns
< 1 ns
(b) TTL Input Test Waveform
AC Timing Diagram
REF
tPD
FB
tREFpwh
tPWH
2.0V
tREFpwl
Figure 4. AC Timing Diagram
tPWL
0.8V
tSKEWPR
tSKEWPR
tCCJ1-3,4-12
Q
[1:2]Q[0:3]
tSKEWBNK
tSKEWBNK
REF TO DEVICE 1 and 2
tPD
FB DEVICE1
tPDELTA
FB DEVICE2
tPDELTA
[1:2]Q[0:3]
Q
tSKEW0,1
Other Q
tODCV
tODCV
tSKEW0,1
[1:2]Q[0,2]
[1:2]Q[1,3]
.
Notes
14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affects these parameters.
15. Rise and fall times are measured between 2.0V and 0.8V.
16. fNOM must be within the frequency range defined by the same FS state.
17. tPWH is measured at 2.0V. tPWL is measured at 0.8V.
18. UI = unit interval. Examples: 1 UI is a full period. 0.1UI is 10% of period.
19. Measured at 0.5V deviation from starting voltage.
20. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 185 MHz or 10 pF to 200 MHz
21. These figures are for illustration purposes only. The actual ATE loads may vary.
Document Number: 38-07336 Rev. *F
Page 9 of 11
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