CY7C144AV(2011) データシートの表示（PDF） - Cypress Semiconductor

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CY7C144AV
(Rev.:2011)

3.3V 8K/16K x 8 Dual-Port Static RAM

Cypress Semiconductor 

CY7C144AV

CY7C006AV

Data Retention Mode

The CY7C144AV and CY7C006AV are designed with battery

backup in mind. Data retention voltage and supply current are

guaranteed over temperature. The following rules ensure data

retention:

1. Chip enable (CE) must be held HIGH during data retention,

within VCC to VCC – 0.2 V.

2. CE must be kept between VCC – 0.2 V and 70% of VCC during

the power-up and power-down transitions.

3. The RAM can begin operation >tRC after VCC reaches the

minimum operating voltage (3.0 volts).

Timing

VCC

CE

Data Retention Mode

3.0 V VCC 2.0 V 3.0 V

tRC

VCC to VCC – 0.2 V

VIH

Parameter

Test Conditions[18]

Max

Unit

ICCDR1

@ VCCDR = 2 V

50

A

Notes

18. CE = VCC, Vin = GND to VCC, TA = 25 °C. This parameter is guaranteed but not tested.

Document #: 38-06051 Rev. *E

Page 10 of 21

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