CY7C144AV(2011) データシートの表示（PDF） - Cypress Semiconductor
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CY7C144AV Datasheet PDF : 21 Pages
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Switching Characteristics Over the Operating Range[8] (continued)
Parameter
Description
tHD
Data hold from write end
tHZWE[13, 14]
R/W LOW to High Z
tLZWE[13, 14]
R/W HIGH to Low Z
tWDD[15]
Write pulse to data delay
tDDD[15]
Write data valid to read data valid
BUSY TIMING[16]
tBLA
BUSY LOW from address match
tBHA
BUSY HIGH from address mismatch
tBLC
BUSY LOW from CE LOW
tBHC
BUSY HIGH from CE HIGH
tPS
Port set-up for priority
tWB
R/W HIGH after BUSY (Slave)
tWH
R/W HIGH after BUSY HIGH (Slave)
tBDD[17]
BUSY HIGH to data valid
INTERRUPT TIMING[16]
tINS
INT set time
tINR
INT reset time
SEMAPHORE TIMING
tSOP
tSWRD
tSPS
tSAA
SEM flag update pulse (OE or SEM)
SEM flag write to read time
SEM flag contention window
SEM address access time
CY7C144AV
CY7C006AV
-25
Min
Max
0
–
15
3
–
–
50
–
35
–
20
–
20
–
20
–
17
5
–
0
–
17
–
–
25
–
20
–
20
12
–
5
–
5
–
–
25
CY7C144AV
CY7C006AV
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
13. Test conditions used are Load 3.
14. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy
waveform.
15. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
16. Test conditions used are Load 2.
17. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
Document #: 38-06051 Rev. *E
Page 9 of 21
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