CY7C017A データシートの表示（PDF） - Cypress Semiconductor
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CY7C017A Datasheet PDF : 20 Pages
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CY7C006A/CY7C007A
CY7C016A/CY7C017A
Switching Characteristics Over the Operating Range[12]
CY7C006A
CY7C007A
CY7C016A
CY7C017A
–12[1]
–15
–20
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
tACE[13]
Output Hold From Address Change
CE LOW to Data Valid
tDOE
tLZOE[14, 15, 16]
tHZOE[14, 15, 16]
tLZCE[14, 15, 16]
tHZCE[14, 15, 16]
tPU[16]
tPD[16]
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
WRITE CYCLE
12
15
20
ns
12
15
20
ns
3
3
3
ns
12
15
20
ns
8
10
12
ns
3
3
3
ns
10
10
12
ns
3
3
3
ns
10
10
12
ns
0
0
0
ns
12
15
20
ns
tWC
tSCE[13]
Write Cycle Time
CE LOW to Write End
tAW
Address Valid to Write End
tHA
tSA[13]
Address Hold From Write End
Address Set-Up to Write Start
tPWE
Write Pulse Width
tSD
Data Set-Up to Write End
tHD[19]
Data Hold From Write End
tHZWE[15, 16]
R/W LOW to High Z
tLZWE[15, 16]
R/W HIGH to Low Z
tWDD[17]
Write Pulse to Data Delay
tDDD[17]
Write Data Valid to Read Data Valid
BUSY TIMING[18]
12
15
20
ns
10
12
15
ns
10
12
15
ns
0
0
0
ns
0
0
0
ns
10
12
15
ns
10
10
15
ns
0
0
0
ns
10
10
12
ns
3
3
3
ns
25
30
45
ns
20
25
30
ns
tBLA
BUSY LOW from Address Match
12
15
20
ns
tBHA
BUSY HIGH from Address Mismatch
12
15
20
ns
tBLC
BUSY LOW from CE LOW
12
15
20
ns
tBHC
BUSY HIGH from CE HIGH
12
15
17
ns
tPS
Port Set-Up for Priority
5
5
5
ns
Notes:
12. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
13. To access RAM, CE = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
14. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
15. Test conditions used are Load 3.
16. This parameter is guaranteed but not tested.
17. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
18. Test conditions used are Load 2.
19. For 15 ns industrial parts tHD Min. is 0.5 ns.
Document #: 38-06045 Rev. *C
Page 8 of 20
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