CY7C026AV-25AXC データシートの表示（PDF） - Cypress Semiconductor
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CY7C026AV-25AXC Datasheet PDF : 19 Pages
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CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
3.3V 4K/8K/16K x 16/18 Dual-Port
Static RAM
Features
■ True dual-ported memory cells which enable simultaneous
access of the same memory location
■ 4, 8 or 16K × 16 organization
■ (CY7C024AV/024BV [1]/ 025AV/026AV)
■ 4 or 8K × 18 organization (CY7C0241AV/0251AV)
■ 16K × 18 organization (CY7C036AV)
■ 0.35 micron CMOS for optimum speed and power
■ High speed access: 20 and 25 ns
■ Low operating power
❐ Active: ICC = 115 mA (typical)
❐ Standby: ISB3 = 10 μA (typical)
Logic Block Diagram
R/WL
UBL
■ Fully asynchronous operation
■ Automatic power down
■ Expandable data bus to 32 bits, 36 bits or more using Master
and Slave chip select when using more than one device
■ On chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flag for port-to-port communication
■ Separate upper byte and lower byte control
■ Pin select for Master or Slave (M/S)
■ Commercial and industrial temperature ranges
■ Available in 100-pin Pb-free TQFP and 100-pin TQFP
R/WR
UBR
CEL
LBL
OEL
[2]
8/9
IO8/9L–IO15/17L
IO0L–IO7[/83L]
8/9
IO
Control
IO
Control
CER
LBR
OER
8/9
[2]
IO8/9L–IO15/17R
8/9
[3]
IO0L–IO7/8R
A0L–A[141]/1213L
12/13/14 Address
Decode
True Dual-Ported
RAM Array
[4]
12/13/14
A0L–A11/12/13L
CEL
Interrupt
OEL
Semaphore
R/WL
Arbitration
SEML [5]
BUSYL
INTL
UBL
LBL
M/S
Notes
1. CY7C024AV and CY7C024BV are functionally identical.
2. IO8–IO15 for x16 devices; IO9–IO17 for x18 devices.
3. IO0–IO7 for x16 devices; IO0–IO8 for x18 devices.
4. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.
5. BUSY is an output in master mode and an input in slave mode.
Address 12/13/14
Decode
12/13/14
[4]
A0R–A11/12/13R
[4]
A0R–A11/12/13R
CER
OER
R/WR
[5] SEMR
BUSYR
INTR
UBR
LBR
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-06052 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 10, 2008
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