AM29BDS323D(2001) データシートの表示（PDF） - Advanced Micro Devices

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AM29BDS323D
(Rev.:2001)

32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory

Advanced Micro Devices 

PRELIMINARY

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

addresses are changed. While in sleep mode, output

data is latched and always available to the system.

ICC4 in the DC Characteristics table represents the

automatic sleep mode current specification.

Accelerated Program Operation

The device offers accelerated program operations

through VPP. This function is primarily intended to

allow faster manufacturing throughput at the factory. If

the system asserts VID on this input, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the input to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

VID from the VPP input returns the device to normal op-

eration. Note that sectors must be unlocked using the

Sector Lock/Unlock command sequence prior to rais-

ing VPP to VID.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Functions and Au-

toselect Command Sequence sections for more

information.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# inputs are both held at VCC ± 0.2 V.

The device requires standard access time (tCE) for

read access when the device is in either of these

standby modes, before it is ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

ICC3 in the DC Characteristics table represents the

standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for tACC +

60 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when

RESET#: Hardware Reset Input

The RESET# input provides a hardware method of re-

setting the device to reading array data. When

RESET# is driven low for at least a period of tRP, the

device immediately terminates any operation in

progress, tristates all outputs, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was

interrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS±0.2 V, the device

draws CMOS standby current (ICC4). If RESET# is

held at VIL but not within VSS±0.2 V, the standby cur-

rent will be greater.

RESET# may be tied to the system reset circuitry. A

system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware from

the Flash memory. Note that RESET# must be as-

serted low during device power-up for proper

operation.

If RESET# is asserted during a program or erase op-

eration, the device requires a time of tREADY (during

Embedded Algorithms) before the device is ready to

read data again. If RESET# is asserted when a pro-

gram or erase operation is not executing, the reset

operation is completed within a time of tREADY (not

during Embedded Algorithms). The system can read

data tRH after RESET# returns to VIH.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 11 for the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device

is disabled. The outputs are placed in the high

impedance state.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 4 for com-

mand definitions).

The device offers three types of data protection at the

sector level:

s The sector lock/unlock command sequence dis-

ables or re-enables both program and erase opera-

tions in any sector.

Am29BDS323D

11

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