AM29BDS323D(2001) データシートの表示（PDF） - Advanced Micro Devices

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AM29BDS323D
(Rev.:2001)

32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory

Advanced Micro Devices 

PRELIMINARY

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Simultaneous Operation Circuit Block Diagram . 5

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6

Special Handling Instructions for FBGA Package .................... 6

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Device Bus Operations ......................................................9

Requirements for Asynchronous Read Operation (Non-Burst) 9

Requirements for Synchronous (Burst) Read Operation .......... 9

Programmable Wait State ...................................................... 10

Power Saving Function ........................................................... 10

Simultaneous Read/Write Operations with Zero Latency ....... 10

Writing Commands/Command Sequences ............................ 10

Accelerated Program Operation ......................................................11

Autoselect Functions .......................................................................11

Automatic Sleep Mode ........................................................... 11

RESET#: Hardware Reset Input ............................................. 11

Output Disable Mode .............................................................. 11

Hardware Data Protection ...................................................... 11

Low VCC Write Inhibit .....................................................................12

Write Pulse “Glitch” Protection ........................................................12

Logical Inhibit ..................................................................................12

Table 2. Sector Address Table ........................................................13

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 15

Reading Array Data ................................................................ 15

Set Wait State Command Sequence ...................................... 15

Table 3. Third Cycle Address/Data .................................................15

Enable PS (Power Saving) Mode Command Sequence ........ 15

Sector Lock/Unlock Command Sequence .............................. 15

Reset Command ..................................................................... 15

Autoselect Command Sequence ............................................ 16

Program Command Sequence ............................................... 16

Unlock Bypass Command Sequence ..............................................16

Figure 1. Program Operation .......................................................... 17

Chip Erase Command Sequence ........................................... 17

Sector Erase Command Sequence ........................................ 17

Erase Suspend/Erase Resume Commands ........................... 18

Figure 2. Erase Operation............................................................... 19

Command Definitions ............................................................. 20

Table 4. Command Definitions .......................................................20

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 21

DQ7: Data# Polling ................................................................. 21

Figure 3. Data# Polling Algorithm ................................................... 21

DQ6: Toggle Bit I .................................................................... 22

Figure 4. Toggle Bit Algorithm........................................................ 22

DQ2: Toggle Bit II ................................................................... 23

Table 5. DQ6 and DQ2 Indications ................................................ 23

Reading Toggle Bits DQ6/DQ2 ............................................... 23

DQ5: Exceeded Timing Limits ................................................ 23

DQ3: Sector Erase Timer ....................................................... 24

Table 6. Write Operation Status ..................................................... 24

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 25

Figure 5. Maximum Negative Overshoot Waveform ...................... 25

Figure 6. Maximum Positive Overshoot Waveform........................ 25

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 25

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 7. Test Setup....................................................................... 27

Table 7. Test Specifications ........................................................... 27

Figure 8. Input Waveforms and Measurement Levels ................... 27

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28

Synchronous/Burst Read ........................................................ 28

Figure 9. Burst Mode Read ............................................................ 28

Asynchronous Read ............................................................... 29

Figure 10. Asynchronous Mode Read............................................ 29

Figure 11. Reset Timings............................................................... 30

Erase/Program Operations ..................................................... 31

Figure 12. Program Operation Timings.......................................... 32

Figure 13. Chip/Sector Erase Operations ...................................... 33

Figure 14. Accelerated Unlock Bypass Programming Timing........ 34

Figure 15. Data# Polling Timings (During Embedded Algorithm) .. 35

Figure 16. Toggle Bit Timings (During Embedded Algorithm)........ 35

Figure 17. Latency with Boundary Crossing .................................. 36

Figure 18. Initial Access with Power Saving (PS)

Function and Address Boundary Latency ...................................... 37

Figure 19. Initial Access with Address Boundary Latency ............. 37

Figure 20. Example of Five Wait States Insertion .......................... 38

Figure 21. Back-to-Back Read/Write Cycle Timings ...................... 39

Erase and Programming Performance . . . . . . . 40

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 41

FDD047—47-Pin Fine-Pitch Ball Grid Array (FBGA)

7 x 10 mm package ................................................................ 41

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 43

Revision A (February 15, 2000) .............................................. 43

Revision B (June 20, 2000) .................................................... 43

Revision B+1 (November 27, 2000) ....................................... 43

Revision B+2 (November 30, 2000) ....................................... 43

Revision B+3 (December 21, 2000) ....................................... 43

Revision B+4 (September 4, 2001) ........................................ 43

Am29BDS323D

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