CY7C037AV-20AXC(2011) データシートの表示（PDF） - Cypress Semiconductor
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CY7C037AV-20AXC Datasheet PDF : 22 Pages
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CY7C027V/027AV/028V
CY7C037AV/038V
OUTPUT
C = 30 pF
3.3 V
R1 = 590
R2 = 435
Figure 3. AC Test Loads and Waveforms
OUTPUT
RTH = 250
C = 30 pF
OUTPUT
VTH = 1.4 V
C = 5 pF
3.3 V
R1 = 590
R2 = 435
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, & tLZWE
including scope and jig)
3.0V
GND
10%
90%
90%
10%
3 ns
Switching Characteristics Over the Operating Range[12]
3 ns
Parameter
Description
CY7C027V/027AV/028V/
CY7C037AV/CY7C038V
-15
-20
-25
Unit
Min Max Min Max Min Max
Read Cycle
tRC
tAA
tOHA
tACE[13]
tDOE
tLZOE[14, 15, 16]
tHZOE[14, 15, 16]
tLZCE[14, 15, 16]
tHZCE[14, 15, 16]
tPU[16]
tPD[16]
tABE[13]
Write Cycle
Read cycle time
Address to data valid
Output hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to power-up
CE HIGH to power-down
Byte enable access time
15
–
20
–
25
–
ns
–
15
–
20
–
25
ns
3
–
3
–
3
–
ns
–
15
–
20
–
25
ns
–
10
–
12
–
13
ns
3
–
3
–
3
–
ns
–
10
–
12
–
15
ns
3
–
3
–
3
–
ns
–
10
–
12
–
15
ns
0
–
0
–
0
–
ns
–
15
–
20
–
25
ns
–
15
–
20
–
25
ns
tWC
tSCE[13]
Write cycle time
CE LOW to write end
15
–
20
–
25
–
ns
12
–
16
–
20
–
ns
tAW
Address valid to write end
12
–
16
–
20
–
ns
tHA
tSA[13]
Address hold from write end
Address setup to write start
0
–
0
–
0
–
ns
0
–
0
–
0
–
ns
tPWE
Write pulse width
12
–
17
–
22
–
ns
tSD
Data setup to write end
10
–
12
–
15
–
ns
Notes
12. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
IOI/IOH and 30 pF load capacitance.
13. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
14. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
15. Test conditions used are Load 2.
16. This parameter is guaranteed by design, but it is not production tested. For information on port-to-port delay through RAM cells from writing port to reading port,
refer to Figure 11.
Document #: 38-06078 Rev. *E
Page 8 of 22
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