CY7C0430BV-133BGI(2006) データシートの表示（PDF） - Cypress Semiconductor

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CY7C0430BV-133BGI
(Rev.:2006)

10 Gb/s 3.3V QuadPort™ DSE Family

Cypress Semiconductor 

Port 1 Operation-Control Logic Block Diagram

(Address Readback is independent of CEs)

R/WP1

W

UBP1

CE0P1

CE1P1

LBP1

OEP1

9

I/O9P1–I/O17P1

9

I/O0P1–I/O8P1

Addr.

Read

CY7C0430BV

CY7C0430CV

Port-1

I/O

Control

MRST

16

A0P1–A15P1

CNTRDP1

MKRDP1

MKLDP1

CNTINCP1

CNTLDP1

CNTRSTP1

CLKP1

MRST

CNTINTP1

Priority

Decision

Logic

Document #: 38-06027 Rev. *B

Port 1

Readback

Register

Port 1

Mask Register

Port 1

Counter/

Address

Register

Port 1

Address

Decode

LBP1

UBP1

R/WP1

CE0P1

CE1P1

OEP1

CLKP1

MRST

Port 1

Interrupt

Logic

Port 1

Port 4

64K × 18

QuadPort

DSE Array

Port 2

Port 3

INTP1

Page 4 of 37

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