CY7C04312BV データシートの表示（PDF） - Cypress Semiconductor
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CY7C04312BV Datasheet PDF : 37 Pages
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PORT 1
PORT 2
PORT 4
PORT 3
DATA PATH AGGREGATOR
Processor 1
CY7C0430BV
CY7C04312BV
CY7C04314BV
Pre-processed DATA Path QuadPort
DSE Family
Processed DATA Path
Processor 2
DATA PATH MANAGER FOR
PARALLEL PACKET PROCESSING
PORT 1
PORT 2
Queue #1
Queue #2
PORT 3
PORT 4
DATA CLASSIFICATION ENGINE
Functional Description
The CY7C043XXBV is a family of 10 Gb/s, true four-ported
Datapath Switching Elements with port speeds of up to
133 MHz[1]. The members of the family include 1-Mb
(64K ×18), ½-Mb (32K x18), and ¼-Mb (16K × 18) options. All
four ports may be clocked at independent frequencies from
one another. Simultaneous reads are allowed for accesses to
the same address location; however, simultaneous reading
and writing to the same address is not allowed. Any port can
write to a certain location while other ports are reading that
location simultaneously, if the timing spec for port to port delay
(tCCS) is met. The result of writing to the same location by more
than one port at the same time is undefined.
Data is registered for decreased cycle time. Clock to data valid
tCD2 = 4.2 ns. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address the counter will self-increment the address inter-
nally (more details to follow). The internal write pulse width is
independent of the duration of the R/W input signal. The
internal write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle is required with chip enables asserted
to reactivate the outputs.
The CY7C0430BV (64K × 18 device) is the only member of
the family which contains burst contains for simple array parti-
tioning. Counter enable inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast interleaved memory
Document #: 38-06027 Rev. *A
Page 2 of 37
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