CY7C04312BV データシートの表示（PDF） - Cypress Semiconductor
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CY7C04312BV Datasheet PDF : 37 Pages
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Port 1 Operation-Control Logic Block Diagram
(Address Readback is independent of CEs)
R/WP1
W
UBP1
CE0P1
CE1P1
LBP1
OEP1
9
I/O9P1–I/O17P1
I/O0P1–I/O8P1
9
Addr.
Read
CY7C0430BV
CY7C04312BV
CY7C04314BV
Port-1
I/O
Control
MRST
16
A0P1–A15P1
CNTRDP1[4]
MKRDP1[4]
MKLDP1[4]
CNTINCP1[4]
CNTLDP1[4]
CNTRSTP1[4]
CLKP1
Priority
Decision
Logic
MRST
CNTINTP1[4]
Document #: 38-06027 Rev. *A
Port 1
Readback
Register
Port 1
Mask Register
Port 1
Counter/
Address
Register
Port 1
Address
Decode
LBP1
UBP1
R/WP1
CE0P1
CE1P1
OEP1
CLKP1
MRST
Port 1
Interrupt
Logic
Port 4
16K/32K/64K × 18
QuadPort
DSE Array
Port 2
INTP1
Page 4 of 37
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