A386DX データシートの表示（PDF） - Intel
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A386DX Datasheet PDF : 139 Pages
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Intel386TM DX MICROPROCESSOR
1 PIN ASSIGNMENT
The Intel386 DX pinout as viewed from the top side
of the component is shown by Figure 1-1 Its pinout
as viewed from the Pin side of the component is
Figure 1-2
VCC and GND connections must be made to multi-
ple VCC and VSS (GND) pins Each VCC and VSS
must be connected to the appropriate voltage level
The circuit board should include VCC and GND
planes for power distribution and all VCC and VSS
pins must be connected to the appropriate plane
NOTE
Pins identified as ‘‘N C ’’ should remain completely
unconnected
231630 – 33
231630 – 34
Figure 1-1 Intel386TM DX PGA
Pinout View from Top Side
Figure 1-2 Intel386TM DX PGA
Pinout View from Pin Side
Table 1-1 Intel386TM DX PGA Pinout Functional Grouping
Signal Pin
A2
C4
A3
A3
A4
B3
A5
B2
A6
C3
A7
C2
A8
C1
A9
D3
A10 D2
A11 D1
A12 E3
A13 E2
A14 E1
A15 F1
A16 G1
A17 H1
A18 H2
A19 H3
A20 J1
A21 K1
A22 K2
A23 L1
Signal Pin
A24
L2
A25
K3
A26
M1
A27
N1
A28
L3
A29
M2
A30
P1
A31
N2
ADS
E14
BE0
E12
BE1
C13
BE2
B13
BE3
A13
BS16
C14
BUSY
B9
CLK2
F12
D0
H12
D1
H13
D2
H14
D3
J14
D4
K14
D5
K13
Signal Pin
D6
L14
D7
K12
D8
L13
D9
N14
D10 M12
D11 N13
D12 N12
D13 P13
D14 P12
D15 M11
D16 N11
D17 N10
D18 P11
D19 P10
D20 M9
D21 N9
D22 P9
D23 N8
D24 P7
D25 N6
D26 P5
D27 N5
Signal Pin
D28
M6
D29
P4
D30
P3
D31
M5
DC
A11
ERROR
A8
HLDA
M14
HOLD
D14
INTR
B7
LOCK
C10
M IO
A12
NA
D13
NMI
B8
PEREQ
C8
READY
G13
RESET
C9
VCC
A1
A5
A7
A10
A14
C5
Signal Pin
VCC
C12
D12
G2
G3
G12
G14
L12
M3
M7
M13
N4
N7
P2
P8
VSS
A2
A6
A9
B1
B5
B11
B14
C11
Signal Pin
VSS
WR
NC
F2
F3
F14
J2
J3
J12
J13
M4
M8
M10
N3
P6
P14
B10
A4
B4
B6
B12
C6
C7
E13
F13
5
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