A386DX データシートの表示（PDF） - Intel

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A386DX

32-BIT CHMOS MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT

Intel 

Intel386TM DX MICROPROCESSOR

1 1 PIN DESCRIPTION TABLE

The following table lists a brief description of each pin on the Intel386 DX The following definitions are used in

these descriptions

The named signal is active LOW

I

Input signal

O Output signal

I O Input and Output signal

No electrical connection

For a more complete description refer to Section 5 2 Signal Description

Symbol

CLK2

D31 – D0

A31 – A2

BE0 –BE3

WR

DC

M IO

LOCK

ADS

NA

READY

BS16

HOLD

Type

I

IO

O

O

O

O

O

O

O

I

I

I

I

Name and Function

CLK2 provides the fundamental timing for the Intel386 DX

DATA BUS inputs data during memory I O and interrupt acknowledge

read cycles and outputs data during memory and I O write cycles

ADDRESS BUS outputs physical memory or port I O addresses

BYTE ENABLES indicate which data bytes of the data bus take part in

a bus cycle

WRITE READ is a bus cycle definition pin that distinguishes write

cycles from read cycles

DATA CONTROL is a bus cycle definition pin that distinguishes data

cycles either memory or I O from control cycles which are interrupt

acknowledge halt and instruction fetching

MEMORY I O is a bus cycle definition pin that distinguishes memory

cycles from input output cycles

BUS LOCK is a bus cycle definition pin that indicates that other

system bus masters are denied access to the system bus while it is

active

ADDRESS STATUS indicates that a valid bus cycle definition and

address (W R D C M IO BE0 BE1 BE2 BE3 and

A31 – A2) are being driven at the Intel386 DX pins

NEXT ADDRESS is used to request address pipelining

BUS READY terminates the bus cycle

BUS SIZE 16 input allows direct connection of 32-bit and 16-bit data

buses

BUS HOLD REQUEST input allows another bus master to request

control of the local bus

6

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