CY7C1021D(2009) データシートの表示（PDF） - Cypress Semiconductor
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CY7C1021D Datasheet PDF : 11 Pages
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CY7C1021D
Switching Characteristics (Over the Operating Range) [6]
Parameter
Description
Read Cycle
tpower [7]
VCC(typical) to the first access
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z [8]
OE HIGH to High Z [8, 9]
CE LOW to Low Z [8]
CE HIGH to High Z [8, 9]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low Z
tHZBE
Byte Disable to High Z
Write Cycle [11]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z [8]
WE LOW to High Z [8, 9]
Byte Enable to End of Write
–10 (Industrial)
Min
Max
100
10
10
3
10
5
0
5
3
5
0
10
5
0
5
10
7
7
0
0
7
6
0
3
5
7
–12 (Automotive)
Unit
Min
Max
100
μs
12
ns
12
ns
3
ns
12
ns
6
ns
0
ns
6
ns
3
ns
6
ns
0
ns
12
ns
6
ns
0
ns
6
ns
12
ns
10
ns
10
ns
0
ns
0
ns
10
ns
7
ns
0
ns
3
ns
6
ns
10
ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of AC Test Loads and Waveforms [5] on page 4. Transition is measured when
the outputs enter a high impedance state.
10. This parameter is guaranteed by design and is not tested.
11. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that
terminates the write.
Document #: 38-05462 Rev. *F
Page 5 of 11
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