CY7C1069AV33(2003) データシートの表示（PDF） - Cypress Semiconductor

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CY7C1069AV33
(Rev.:2003)

2M x 8 Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Write Cycle No. 1 (CE1 Controlled)[13, 14, 15]

tWC

ADDRESS

CY7C1069AV33

CE

tSA

tSCE

tAW

WE

DATAI/O

Write Cycle No. 2 (WE Controlled, OE LOW) [13, 14, 15]

tWC

ADDRESS

tPWE

tBW

tSD

tHA

tHD

CE

tSCE

tSA

WE

DATA I/O

tAW

tPWE

tHZWE

tSD

Truth Table

CE1 CE2 OE WE

I/O0–I/O7

H

X

X

X High-Z

Power-down

Mode

X

L

X

X High-Z

Power-down

L

H

L

H Data Out

Read All Bits

L

H

X

L Data In

Write All Bits

L

H

H

H High-Z

Selected, Outputs Disabled

Notes:

12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.

13. Data I/O is high-impedance if OE = VIH.

14. If CE1 goes HIGH / CE2 LOW simultaneously with WE going HIGH, the output remains in a high–impedance state.

15. CE above is defined as a combination of CE1 and CE2. It is active low.

tHA

tHD

tLZWE

Power

Standby (ISB)

Standby (ISB)

Active (ICC)

Active (ICC)

Active (ICC)

Document #: 38-05255 Rev. *D

Page 6 of 9

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