CY7C1316AV18 データシートの表示（PDF） - Cypress Semiconductor
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CY7C1316AV18 Datasheet PDF : 20 Pages
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CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Switching Characteristics Over the Operating Range (continued)[17,18]
Cypress Consortium
Parameter Parameter
Description
250 MHz 200 MHz 167 MHz
Min. Max. Min. Max. Min. Max. Unit
tCQOH
tCHCQX
tCQD
tCQHQV
tCQDOH
tCQHQX
tCHZ
tCHZ
tCLZ
tCLZ
DLL Timing
Echo Clock Hold after C/C Clock Rise
–0.45 – –0.45 – –0.50 – ns
Echo Clock High to Data Valid
– 0.30 – 0.35 – 0.40 ns
Echo Clock High to Data Invalid
–0.30 – –0.35 – –0.40 – ns
Clock (C and C) Rise to High-Z (Active to High-Z)[19, 20] – 0.45 – 0.45 – 0.50 ns
Clock (C and C) Rise to Low-Z[19, 20]
–0.45 – –0.45 – –0.50 – ns
tKC Var
tKC lock
tKC Reset
tKC Var
tKC lock
tKC Reset
Clock Phase Jitter
DLL Lock Time (K, C)
K Static to DLL Reset
– 0.20 – 0.20 – 0.20 ns
1024 – 1024 – 1024 – Cycles
30
30
30
ns
Switching Waveforms[21, 22, 23]
NOP
READ
READ
NOP
NOP
WRITE
WRITE
READ
1
2
3
4
5
6
7
8
9
10
K
tKH tKL
tCYC
tKHKH
K
LD
tSC
tHC
R/W
A
A0
A1
tSA tHA
DQ Qx2
tKHCH
C
tKHCH
tCO
tCLZ
C#
CQ
tCCQO
tCQOH
CQ#
Q00 Q01 Q10 Q11
A2
A3
A4
tHD
tSD
tHD
tSD
D20 D21 D30 D31
tCO
tDOH
tCHZ
tDOH
tKH tKL
tCYC
tKHKH
tCCQO
tCQOH
Q40 Q41
tCQD
DON’T CARE
UNDEFINED
Notes:
19. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
20. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
21. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
22. Output are disabled (High-Z) one clock cycle after a NOP.
23. In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document #: 38-05499 Rev. *B
Page 11 of 20
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