HV623 データシートの表示（PDF） - Supertex Inc
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HV623 Datasheet PDF : 10 Pages
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HV623
– OBSOLETE – Electrical Characteristics
AC Characteristics (VDD = 5.5V, TA = 25°C)
Logic Timing
Symbol
Parameter
Min Typ Max Units
Conditions
fSC
fDIN
tSS
tHS
tWA
tDS
tDH
tWD
tWLC
tDLCR
tDRCC1
tDSL
tCSC
tWSC
tCCC
tWCC
Shift clock operating frequency
Data-in frequency
CSI/CSO pulse to shift clock setup time
CSI/CSO pulse to shift clock hold time
CSI pulse width
Data to shift clock setup time
Data to shift clock hold time
Data-in pulse width
Load count pulse width
Load count to ramp delay
Ramp to count clock delay
Shift clock to load count delay time
Shift clock cycle time
Shift clock pulse width
Count clock cycle time
Count clock pulse width
100
50
120
50
50
100
200
1.0
0.47
200
250
125
250
125
4.0 MHz
4.0 MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
Note 1: Count clock starts counting after 0.47µs min. This is equivalent to a time duration for a linear ramp VR to ramp from 0 to 3V, assuming the minimum value of TRR,
ramp size time of 12µs for VR = 80V.
VRAMP Timing
Symbol
Parameter
tCR
Cycle time of ramp signal
tRR
Ramp rise time
tHR2
Ramp hold time
tFR
Ramp fall time
Min Typ Max Units
15
µs
12
µs
2.0
15
µs
3.0
µs
Note 2: The maximum ramp hold time may be longer than 15 µs, but the output voltage HVOUT will droop due to leakage.
Conditions
CLOAD = 1µF
Table 1:
Schemes to control IPP bias current, typical IPP
Option 1
Option 2
V
BIAS
(V)
V
CTL
(V)
R
CTL
(Ω)
I
PP
(mA)
V
BIAS
(V)
V
CTL
(V)
R
CTL
(Ω)
0
0.1 56K 2.0
-1.0 0 56K
0
1.0 56K 7.0
-2.0 0 56K
I
PP
(mA)
4.0
5.5
VCTL +-
VCTL
HV623
RCTL
RCTL
+- VBIAS
4
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