HV66PG-GM919 データシートの表示（PDF） - Supertex Inc
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HV66PG-GM919 Datasheet PDF : 7 Pages
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HV66
Electrical Characteristics (over recommended operating conditions unless otherwise noted)
DC Characteristics (VDD = 5.0V, VPP = 60V)
Sym Parameter
Min
Max Units Conditions
IDD
VDD supply current
IPPQ
Quiescent VPP supply current
-
15
mA VDD = 5.5V, fCLK = 5.0MHz
-
0.5
mA Outputs high
-
0.5
mA Outputs low
IDDQ
VOH
VOL
IIH
IIL
VOLBP
VOHBP
Quiescent VDD supply current
High-level output
HVOUT
DATA OUT
Low-level output
HVOUT
DATA OUT
High-level input current
Low-level input current
Low-level output voltage, backplane
High-level output voltage, backplane
-
0.5
mA All VIN = GND or VDD
50
-
V
IO = -5.0mA, VPP = +60V
4.6
-
IO = -100µA
-
8.0
V
IO = +5.0mA, VPP = +60V
-
0.4
IO = +100µA
-
1.0
µA VIH = VDD
-
-1.0
µA VIL = 0V
-
3.0
V IO = +10mA
57
-
V IO = -10mA
AC Characteristics (VDD = 5.0V, VPP = 60V, TA = 25OC, logic input rise/fall time = 10ns.)
fCLK
Clock frequency
-
5.0 MHz
tWL, tWH Clock width high or low
100
-
ns
tSU
Data set-up time before clock rises
25
-
ns
tH
Data hold time after clock rises
50
-
ns
tHON, tHOFF Time from latch enable or POL to HVOUT
-
500
ns
tBON, tBOFF Time from POL to BPOUT
-
500
ns
tDHL
Delay time clock to data high to low
-
200
ns
tDLH
Delay time clock to data low to high
-
200
ns
tDLE
Delay time clock to LE low to high
50
-
ns
tWLE
Width of LE pulse
100
-
ns
tSLE
LE set-up time before clock rises
50
-
ns
tBR, tBF BPOUT rise/fall time
10
1000 µs
|tBR - tBF| BPOUT rise and fall difference
-
100
µs
---
---
---
---
CL = 20pF
CL = 20pF
CL = 10pF
CL = 10pF
---
---
---
CL = 350pF
CL = 350pF
Power-up sequence should be the following:
1. Connect ground.
2. Apply VDD.
3. Set all inputs (Data, CLK, EN, etc.) to a known state.
4. Apply VPP.
The VPP should not drop below VDD during operation.
Power-down sequence should be the reverse of the above.
Doc.# DSFP-HV66
C070313
Supertex inc.
3
www.supertex.com
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