AD5532 データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
AD5532 Datasheet PDF : 20 Pages
| |||
AD5532
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Table 3.
Parameter1, 2
t1
t2
t3
t4
t5
t6
Limit at TMIN, TMAX (A Version)
0
0
50
50
20
7
1 See Figure 2 and Figure 3, the parallel interface timing diagrams.
2 Guaranteed by design and characterization, not production tested.
PARALLEL INTERFACE TIMING DIAGRAMS
t1
t2
CS
t3
t4
WR
A4–A0, CAL,
OFFS_SEL
t5
t6
Figure 2. Parallel Write (ISHA Mode Only)
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments
CS to WR setup time
CS to WR hold time
CS pulse width low
WR pulse width low
A4–A0, CAL, OFFS_SEL to WR setup time
A4–A0, CAL, OFFS_SEL to WR hold time
200μA
IOL
TO OUTPUT
PIN CL
50pF
1.6V
200μA
IOH
Figure 3. Load Circuit for DOUT Timing Specifications
Rev. D | Page 6 of 20
Share Link: 