DD28F032SA データシートの表示（PDF） - Intel

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DD28F032SA

32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile™ MEMORY

Intel 

DD28F032SA

E

NOTES:

1. See AC Input/Output Reference Waveforms for timing measurements, Figures 6 and 7.

2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CEX# without impact in tELQV.

3. Sampled, not 100% tested.

4. This timing parameter is used to latch the correct BSR data onto the outputs.

5. Device speeds are defined as:

70/80 ns at VCC = 5.0V equivalent to

150 ns at VCC = 3.3V

100 ns at VCC = 5.0V equivalent to

150 ns at VCC = VCC = 3.3V

6. See AC Input/Output Reverence Waveforms and AC Testing Load Circuits for High Speed Test Configuration.

7. See Standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.

VIH

ADDRESSES (A)

VIL

V IH

ADDRESSES STABLE

t AVAV

CEx# (E)(1)

V IL

t AVEL

t EHQZ

VIH

OE# (G)

VIL

t AVGL

t GHQZ

VIH

WE# (W)

VIL

VOH

DATA (D/Q)

VOL

5.0V

VCC

GND

VIH

HIGH Z

t ELQV

tGLQX

tELQX

t GLQV

t AVQV

t

PHQV

t

OH

VALID OUTPUT

HIGH Z

RP# (P)

VIL

NOTES:

For 28F016SA No. 1: CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.

For 28F016SA No. 2: CEX# is defined as the latter of CE0# or CE2# going low, or the first of CE0# or CE2# going high.

0490-11

Figure 11. Read Timing Waveforms

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