CY7C1327G-100AXC データシートの表示（PDF） - Cypress Semiconductor
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CY7C1327G-100AXC Datasheet PDF : 18 Pages
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PRELIMINARY
CY7C1327G
Pin Definitions
Name
A0, A1, A
BWA,BWB
GW
BWE
CLK
CE1
CE2
CE3
OE
ADV
ADSP
ZZ
ADSC
DQA,
DQB
DQPA,
DQPB
VDD
VSS
VDDQ
MODE
NC
I/O
Description
Input-
Address Inputs used to select one of the 256K address locations. Sampled at the rising edge
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0
feed the 2-bit counter.
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
Input-
Synchronous
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is
loaded.
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device. Not connected for BGA. Where referenced, CE3 is
assumed active throughout this document for BGA. CE3 is sampled only when a new external
address is loaded.
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Input-
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
Synchronous automatically increments the address in a burst cycle.
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1
is deasserted HIGH.
Input-
ZZ “sleep” Input, active HIGH. This input, when High places the device in a non-time-critical
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
Synchronous asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only ADSP is recognized.
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by “A” during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and
DQP[A:B] are placed in a tri-state condition.
Power Supply Power supply inputs to the core of the device.
Ground Ground for the device.
I/O Ground Ground for the I/O circuitry.
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
No Connects. Not internally connected to the die.
Document #: 38-05519 Rev. *A
Page 4 of 18
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