CY7C1345F-100AC データシートの表示（PDF） - Cypress Semiconductor
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CY7C1345F-100AC Datasheet PDF : 17 Pages
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Pin Configurations (continued)
1
A
VDDQ
B
NC
C
NC
D
DQC
E
DQC
F
VDDQ
G
DQC
H
DQC
J
VDDQ
K
DQD
L
DQD
M
VDDQ
N
DQD
P
DQD
R
NC
T
NC
U
VDDQ
2
A
CE2
A
DQPC
DQC
DQC
DQC
DQC
VDD
DQD
DQD
DQD
DQD
DQPD
A
NC
NC
119-Ball BGA
3
A
A
A
VSS
VSS
VSS
BWC
VSS
NC
VSS
BWD
VSS
VSS
VSS
MODE
A
NC
4
ADSP
ADSC
VDD
NC
CE1
OE
ADV
GW
VDD
CLK
NC
BWE
A1
A0
VDD
A
NC
5
A
A
A
VSS
VSS
VSS
BWB
VSS
NC
VSS
BWA
VSS
VSS
VSS
NC
A
NC
CY7C1345F
6
A
CE3
A
DQPB
DQB
DQB
DQB
DQB
VDD
DQA
DQA
DQA
DQA
DQPA
A
NC
NC
7
VDDQ
NC
NC
DQB
DQB
VDDQ
DQB
DQB
VDDQ
DQA
DQA
VDDQ
DQA
DQA
NC
ZZ
VDDQ
Pin Descriptions
Name
A0, A1, A
BWA,BWB
BWC,BWD
GW
TQFP
37,36,32,
33,34,35,
44,45,46,
47,48,49,
50,81,82,
99,100
93,94,
95,96
88
BWE
87
CLK
89
CE1
98
CE2
97
CE3
92
BGA
I/O
Description
P4,N4,A2,A3, Input- Address Inputs used to select one of the 128K address
A5,A6,B3,B5, Synchronous locations. Sampled at the rising edge of the CLK if ADSP or ADSC
C2,C3,C5,C6,
R2,R6,T3,T4,
is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed
the 2-bit counter.
T5
L5,G5,
G3,L3
H4
M4
K4
E4
B2
B6
Input- Byte Write Select Inputs, active LOW. Qualified with BWE to
Synchronous conduct byte writes to the SRAM. Sampled on the rising edge of CLK.
Input- Global Write Enable Input, active LOW. When asserted LOW on
Synchronous the rising edge of CLK, a global write is conducted (ALL bytes are
written, regardless of the values on BW[A:D] and BWE).
Input- Byte Write Enable Input, active LOW. Sampled on the rising edge
Synchronous of CLK. This signal must be asserted LOW to conduct a byte write.
Input-Clock Clock Input. Used to capture all synchronous inputs to the device.
Also used to increment the burst counter when ADV is asserted
LOW, during a burst operation.
Input- Chip Enable 1 Input, active LOW. Sampled on the rising edge of
Synchronous CLK. Used in conjunction with CE2 and CE3 to select/deselect the
device. ADSP is ignored if CE1 is HIGH.
Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of
Synchronous CLK. Used in conjunction with CE1 and CE3 to select/deselect the
device.
Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK.
Synchronous Used in conjunction with CE1 and CE2 to select/deselect the device.
Document #: 38-05214 Rev. *C
Page 3 of 17
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