CY7C1361A データシートの表示（PDF） - Cypress Semiconductor
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CY7C1361A Datasheet PDF : 26 Pages
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CY7C1361A
CY7C1363A
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
controller’s capture set-up plus hold time (tCS plus tCH). The
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
Moving the controller to Shift-DR state then places the
boundary scan register between the TDI and TDO pins.
Because the PRELOAD portion of the command is not imple-
mented in this device, moving the controller to the Update-DR
state with the SAMPLE/PRELOAD instruction loaded in the
instruction register has the same effect as the Pause-DR
command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP controller is in the Shift-DR state, the
bypass register is placed between TDI and TDO. This allows
the board level scan path to be shortened to facilitate testing
of other devices in the scan path.
Reserved
Do not use these instructions. They are reserved for future
use.
1
TEST-LOGIC
RESET
0
0
REUN-TEST/ 1
IDLE
SELECT
1
DR-SCAN
1
SELECT
IR-SCAN
0
1
CAPTURE-DR
0
1
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
1
EXIT1-IR
1
0
0
PAUSE-DR
0
PAUSE-IR
0
1
0
EXIT2-DR
1
1
0
EXIT2-IR
1
UPDATE-DR
1
0
Figure 1. TAP Controller State Diagram[11]
Note:
11. The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK.
UPDATE-IR
1
0
Document #: 38-05259 Rev. *A
Page 11 of 26
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