CY7C1361C-133AJXC(2006) データシートの表示（PDF） - Cypress Semiconductor
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CY7C1361C-133AJXC Datasheet PDF : 31 Pages
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CY7C1361C
CY7C1363C
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
Comm/ind’l
Automotive
50
mA
60
mA
tZZS
tZZREC
tZZI
tRZZI
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
2tCYC
ns
2tCYC
ns
2tCYC
ns
0
ns
Truth Table [3, 4, 5, 6, 7]
Cycle Description
Address
Used CE1 CE2 CE3 ZZ
Deselected Cycle, Power-down None H X X L
Deselected Cycle, Power-down None L L X L
Deselected Cycle, Power-down None L X H L
Deselected Cycle, Power-down None L L X L
Deselected Cycle, Power-down None X X X L
Sleep Mode, Power-down
None X X X H
Read Cycle, Begin Burst
External L H L L
Read Cycle, Begin Burst
External L H L L
Write Cycle, Begin Burst
External L H L L
Read Cycle, Begin Burst
External L H L L
Read Cycle, Begin Burst
External L H L L
Read Cycle, Continue Burst
Next X X X L
Read Cycle, Continue Burst
Next X X X L
Read Cycle, Continue Burst
Next H X X L
Read Cycle, Continue Burst
Next H X X L
Write Cycle, Continue Burst
Next X X X L
Write Cycle, Continue Burst
Next H X X L
Read Cycle, Suspend Burst Current X X X L
Read Cycle, Suspend Burst Current X X X L
Read Cycle, Suspend Burst Current H X X L
Read Cycle, Suspend Burst Current H X X L
Write Cycle, Suspend Burst Current X X X L
Write Cycle, Suspend Burst Current H X X L
ADSP
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSC ADV WRITE OE CLK
L
X
X X L-H
X
X
X X L-H
X
X
X X L-H
L
X
X X L-H
L
X
X X L-H
X
X
X XX
X
X
X
L L-H
X
X
X H L-H
L
X
L
X L-H
L
X
H
L L-H
L
X
H H L-H
H
L
H
L L-H
H
L
H H L-H
H
L
H
L L-H
H
L
H H L-H
H
L
L
X L-H
H
L
L
X L-H
H
H
H L L-H
H
H
H H L-H
H
H
H L L-H
H
H
H H L-H
H
H
L
X L-H
H
H
L
X L-H
DQ
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Q
Tri-state
D
Q
Tri-state
Q
Tri-state
Q
Tri-state
D
D
Q
Tri-state
Q
Tri-state
D
D
Notes:
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't
care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05541 Rev. *F
Page 10 of 31
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