24LC32-/SM データシートの表示（PDF） - Microchip Technology
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24LC32-/SM Datasheet PDF : 14 Pages
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24LC32
TABLE 1-3: AC CHARACTERISTICS
Parameter
VCC = 2.5V-6.0V VCC = 4.5 - 6.0V
Symbol STD. MODE FAST MODE Units
Remarks
Min Max Min Max
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
FCLK
—
100
—
400
THIGH
4000
—
600
—
TLOW
4700
—
1300
—
TR
—
1000
—
300
TF
—
300
—
300
THD:STA 4000
—
600
—
START condition setup time TSU:STA 4700
—
600
—
Data input hold time
THD:DAT
0
—
0
—
Data input setup time
TSU:DAT 250
—
100
—
STOP condition setup time TSU:STO 4000
—
600
—
Output valid from clock
TAA
—
3500
—
900
Bus free time
TBUF
4700
—
1300
—
Output fall time from VIH min
TOF
to VIL max
Input filter spike suppression
TSP
(SDA and SCL pins)
—
250 20 +0.1 250
CB
—
50
—
50
kHz
ns
ns
ns (Note1)
ns (Note1)
ns After this period the first clock
pulse is generated
ns Only relevant for repeated
START condition
ns
ns
ns
ns (Note 2)
ns Time the bus must be free
before a new transmission can
start
ns (Note 1), CB ≤ 100 pF
ns (Note 3)
Write cycle time
TWR
—
5
—
5 ms/page (Note 4)
Endurance
High Endurance Block
—
Rest of Array
—
10M
—
10M
— cycles 25°C, Vcc = 5.0V, Block Mode
1M
—
1M
—
(Note 5)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a Ti specification for standard operation.
4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.
5: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained from our website.
FIGURE 1-2: BUS TIMING DATA
TF
SCL
TSU:STA
SDA
IN
SDA
OUT
TSP
TAA
TLOW
THD:STA
THIGH
THD:DAT
TAA
TR
TSU:DAT TSU:STO
TBUF
2004 Microchip Technology Inc.
DS21072G-page 3
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