CY7C185-20PXC データシートの表示（PDF） - Cypress Semiconductor

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CY7C185-20PXC

64-Kbit (8 K × 8) Static RAM

Cypress Semiconductor 

CY7C185

64-Kbit (8 K × 8) Static RAM

Features

■ High speed

❐ 15 ns

■ Fast tDOE

■ Low active power

❐ 715 mW

■ Low standby power

❐ 85 mW

■ CMOS for optimum speed/power

■ Easy memory expansion with CE1, CE2 and OE features

■ TTL-compatible inputs and outputs

■ Automatic power-down when deselected

■ Available in non Pb-free 28-pin (300-Mil) Molded SOJ, 28-pin

(300-Mil) Molded SOIC and Pb-free 28-pin (300-Mil) Molded

DIP

Logic Block Diagram

Functional Description

The CY7C185[1] is a high-performance CMOS static RAM

organized as 8192 words by 8 bits. Easy memory expansion is

provided by an active LOW chip enable (CE1), an active HIGH

chip enable (CE2), and active LOW output enable (OE) and

tri-state drivers. This device has an automatic power-down

feature (CE1 or CE2), reducing the power consumption by 70%

when deselected. The CY7C185 is in a standard 300-mil-wide

DIP, SOJ, or SOIC package.

An active LOW write enable signal (WE) controls the

writing/reading operation of the memory. When CE1 and WE

inputs are both LOW and CE2 is HIGH, data on the eight data

input/output pins (I/O0 through I/O7) is written into the memory

location addressed by the address present on the address pins

(A0 through A12). Reading the device is accomplished by

selecting the device and enabling the outputs, CE1 and OE

active LOW, CE2 active HIGH, while WE remains inactive or

HIGH. Under these conditions, the contents of the location

addressed by the information on address pins are present on the

eight data input or output pins.

The input or output pins remain in a high-impedance state unless

the chip is selected, outputs are enabled, and write enable (WE)

is HIGH. A die coat is used to insure alpha immunity.

I/O0

INPUT BUFFER

I/O1

A1

I/O2

A2

A3

I/O3

A4

8K x 8

A5

ARRAY

A6

I/O4

A7

A8

I/O5

CE1

CE2

POWER

COLUMN DECODER DOWN

WE

OE

I/O6

I/O7

Selection Guide

Description

-15

-20

-35

Maximum Access Time (ns)

15

20

35

Maximum Operating Current (mA)

130

110

100

Maximum CMOS Standby Current (mA)

15

15

15

Note

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation • 198 Champion Court

Document #: 38-05043 Rev. *E

• San Jose, CA 95134-1709 • 408-943-2600

Revised April 20, 2011

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