CY7C185-20PXC データシートの表示（PDF） - Cypress Semiconductor

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CY7C185-20PXC

64-Kbit (8 K × 8) Static RAM

Cypress Semiconductor 

Switching Waveforms (continued)

Figure 4. Write Cycle No. 1 (WE Controlled)[9,11]

tWC

ADDRESS

CE1

tSCEI

tAW

tHA

CCEE2

tSA

WE

tSCE2

tPWE

OE

DATA I/O

ADDRESS

CE1

CE2

WE

DATA I/O

NOTE 12

tHZOE

tSD

tHD

DATA IN VALID

Figure 5. Write Cycle No. 2 (CE Controlled)[11,12,13]

tWC

tSCE1

tSA

tSCE2

tAW

tHA

tSD

tHD

DATA IN VALID

CY7C185

Notes

12. During this period, the I/Os are in the output state and input signals must not be applied.

13. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

Document #: 38-05043 Rev. *E

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