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CY7C197BN(2011) データシートの表示(PDF) - Cypress Semiconductor

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CY7C197BN
(Rev.:2011)
Cypress
Cypress Semiconductor Cypress
CY7C197BN Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
256-Kb (256 K × 1) Static RAM
Features
Fast access time: 15 ns
Wide voltage range: 5.0 V ± 10% (4.5 V to 5.5 V)
CMOS for optimum speed and power
TTL compatible inputs and outputs
Available in 24-pin DIP and 24-pin SOJ
Logic Block Diagram
Input
Buffer
CY7C197BN
256-Kb (256 K × 1) Static RAM
General Description [1]
The CY7C197BN is a high performance CMOS Asynchronous
SRAM organized as 256 K × 1 bits that supports an
asynchronous memory interface. The device features an
automatic power down feature that significantly reduces power
consumption when deselected.
See the Truth Table on page 8 for a complete description of Read
and Write modes.
The CY7C197BN is available in 24-pin DIP and 24-pin SOJ
package(s).
Din
RAM Array
Dout
Column
Decoder
Product Portfolio
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Power
Down
Circuit
-15
15
150
10
CE
WE
x Ax
-25
25
95
10
Unit
ns
mA
mA
Note
1. For best practice recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-06447 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 6, 2011
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