STK14C88-K25 データシートの表示（PDF） - Simtek Corporation
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STK14C88-K25 Datasheet PDF : 13 Pages
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STK14C88
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1, #2
Alt.
PARAMETER
STK14C88-25
MIN MAX
1
tELQV
2
tAVAVg
3
tAVQVh
4
tGLQV
5
tAXQXh
6
tELQX
7
tEHQZi
8
tGLQX
9
tGHQZi
10
tELICCHf
11
tEHICCLf
tACS
tRC
tAA
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
25
25
25
10
5
5
10
0
10
0
25
Note g: W and HSB must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: I/O state assumes E and G < VIL and W > VIH; device is continuously selected.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
(VCC = 5.0V ± 10%)e
STK14C88-35
MIN MAX
STK14C88-45
UNITS
MIN MAX
35
45
ns
35
45
ns
35
45
ns
15
20
ns
5
5
ns
5
5
ns
13
15
ns
0
0
ns
13
15
ns
0
0
ns
35
45
ns
ADDRESS
DQ (DATA OUT)
5
tAXQX
2
tAVAV
3
tAVQV
DATA VALID
SRAM READ CYCLE #2: E Controlledg
ADDRESS
E
6
tELQX
2
tAVAV
1
tELQV
G
DQ (DATA OUT)
ICC
8
tGLQX
4
tGLQV
10
tELICCH
STANDBY
ACTIVE
11
tEHICCL
7
tEHQZ
9
tGHQZ
DATA VALID
December 2002
3 Document Control # ML0014 rev 0.0
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