CY7C4241-15AXC データシートの表示（PDF） - Cypress Semiconductor
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CY7C4241-15AXC Datasheet PDF : 19 Pages
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CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms (continued)
Reset Timing[17]
RS
REN1,
REN2
WEN1
WEN2/LD[18]
EF,PAE
FF,PAF,
Q0 - Q8
tRS
tRSS
tRSS
tRSS
tRSF
tRSF
tRSF
tRSR
tRSR
tRSR
First Data Word Latency after Reset with Simultaneous Read and Write
OE = 1[19]
OE = 0
WCLK
tDS
D0–D8
D0 (FIRSTVALID Write)
D1
tENS
WEN1
WEN2
(if applicable)
[20]
tFRL
RCLK
tSKEW1
tREF
EF
REN1,
REN2
D2
tA[21]
D3
D4
tA
Q0 –Q8
OE
tOLZ
tOE
D0
D1
Notes:
17. The clocks (RCLK, WCLK) can be free-running during reset.
18. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
for the programmable flag offset registers.
19. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
20. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or
tCLK + tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW).
21. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06016 Rev. *C
Page 10 of 19
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