CY7C4241-15AXC データシートの表示（PDF） - Cypress Semiconductor
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CY7C4241-15AXC Datasheet PDF : 19 Pages
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CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Selection Guide
-10
-15
-25
Unit
Maximum Frequency
100
66.7
40
MHz
Maximum Access Time
8
10
15
ns
Minimum Cycle Time
10
15
25
ns
Minimum Data or Enable Set-up
3
4
6
ns
Minimum Data or Enable Hold
0.5
1
1
ns
Maximum Flag Delay
8
10
15
ns
Active Power Supply Current
Commercial
35
35
35
ICC1
Industrial
40
40
40
Density
CY7C4421
64 × 9
CY7C4201
256 × 9
CY7C4211
512 × 9
CY7C4221
1K × 9
CY7C4231
2K × 9
CY7C4241
4K × 9
CY7C4251
8K × 9
Pin Definitions
Pin
D0–8
Q0–8
WEN1
Name
Data Inputs
Data Outputs
Write Enable 1
WEN2/LD Dual Write Enable 2
Mode Pin
Load
REN1, REN2
WCLK
Read Enable
Inputs
Write Clock
RCLK
Read Clock
EF
Empty Flag
FF
Full Flag
PAE
Programmable
Almost Empty
PAF
Programmable
Almost Full
RS
Reset
OE
Output Enable
I/O
Description
I Data Inputs for 9-bit Bus
O Data Outputs for 9-bit Bus
I The only Write enable to have programmable flags when device is configured. Data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two Write enables, data is written on a LOW-to-HIGH
transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
I If HIGH at reset, this pin operates as a second Write enable. If LOW at reset, this pin
I
operates as a control to Write or Read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into
the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags,
WEN2/LD is held LOW to write or read the programmable flag offsets.
I Enables Device for Read Operation
I The rising edge clocks data into the FIFO when WEN1 is LOW, WEN2/LD is HIGH, and
the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
I The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the
FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable
flag-offset register.
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO.
O When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO.
I Resets device to empty condition. A reset is required before an initial Read or Write
operation after power-up.
I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected.
If OE is HIGH, the FIFO’s outputs are in High-Z (high-impedance) state.
Document #: 38-06016 Rev. *C
Page 2 of 19
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