CY7C4241-15AXC データシートの表示（PDF） - Cypress Semiconductor
部品番号
コンポーネント説明
メーカー
CY7C4241-15AXC Datasheet PDF : 19 Pages
| |||
Switching Waveforms
Write Cycle Timing
WCLK
D0 –D8
WEN1
tCLKH
tCLK
tCLKL
tDS
tENS
WEN2
(if applicable)
FF
RCLK
tWFF
tSKEW1[15]
REN1,REN2
Read Cycle Timing
RCLK
REN1,REN2
tENS
EF
Q0 –Q8
OE
tOLZ
WCLK
WEN1
tCLKH
tCKL
tCLKL
tENH
tREF
tA
NO OPERATION
tOE
[16]
tSKEW1
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
tDH
tENH
tWFF
NO OPERATION
NO OPERATION
tREF
VALID DATA
tOHZ
WEN2
Notes:
15. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time
between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
16. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time
between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK rising edge.
Document #: 38-06016 Rev. *C
Page 9 of 19
Share Link: 