CY7C441-14JC データシートの表示（PDF） - Cypress Semiconductor
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CY7C441-14JC Datasheet PDF : 15 Pages
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CY7C441
CY7C443
ENR and ENW are HIGH). Upon completion of the Master
Reset cycle, all data outputs will go LOW tAMR after MR is
deasserted. F1 and F2 are guaranteed to be valid tMRF after
MR is taken HIGH.
FIFO Operation
When the ENW signal is active (LOW), data on the D0–8 pins
is written into the FIFO on each rising edge of the CKW signal.
Similarly, when the ENR signal is active, data in the FIFO
memory will be presented on the Q0–8 outputs. New data will
be presented on each rising edge of CKR while ENR is active.
ENR must set up tSEN before CKR for it to be a valid read.
ENW must occur tSEN before CKW for it to be a valid write.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0–8 outputs
even after additional reads occur.
Flag Operation
The CY7C441/3 provide two flags, F1 and F2, which are used
to decode four FIFO states (see Table 1). All flags are synchro-
nous, meaning that the change of states is relative to one of
the clocks (CKR or CKW, as appropriate; see Figure 1). The
synchronous architecture guarantees some minimum valid
time for the flags.
The Empty and Almost Empty flag states are exclusively up-
dated by each rising edge of the read clock (CKR). For exam-
ple, when the FIFO contains 1 word, the next read (rising edge
of CKR while ENR=LOW) causes the F1 and F2 pins to output
a state signifying the Empty condition. The Almost Full flag is
updated exclusively by the write clock (CKW). For example, if
the CY7C443 FIFO contains 2031 words (2032 words or
greater indicates Almost Full in the CY7C443), the next write
(rising edge of CKW while ENW=LOW) causes the F1 and F2
pins to output the Almost Full state.
Table 1. Flag Truth Table
F1 F2
State
CY7C441
Number of
Words in FIFO
00
Empty 0
10
Almost
Empty
1 – 16
1 1 Intermediate 17 – 495
Range
0 1 Almost Full 496 – 512
or Full
CY7C443
Number of
Words in FIFO
0
1 – 16
17 – 2031
2032 – 2048
E
CKR
F1
AF
CKW
AE
F2
CKR
INTERNAL LOGIC
Figure 1. Flag Logic Diagram
PINS
C441-16
Flag Operation (continued)
Since the flags denoting emptiness (Empty, Almost Empty) are
only updated by CKR and the Almost Full flag is only updated
by the CKW, careful attention must be given to the flag opera-
tion. The user must be aware that if a flag boundary (Empty,
Almost Empty, and Almost Full) is crossed due to an operation
from a clock that the flag is not synchronized to (i.e.,CKR does
not effect Almost Full), a flag update is necessary to represent
the FIFO’s new state. This signal to which a flag is not synchro-
nized will be referred to as the opposite clock (CKW is opposite
clock for Empty and Almost Empty flags; CKR is the opposite
clock for the Almost Full flag).
Until the flag update cycle is executed, the synchronous flags
do not show the true state of the FIFO. For example, if 2,040
writes are performed to an empty CY7C443 without a single
read, F1 and F2 will still exhibit an Empty flag. This is because
F2 is exclusively updated by the CKR, therefore, a single read
(flag update cycle) is necessary to update flags to Almost Full
state. It should be noted that this flag update read does not
require ENR = LOW, so a free-running read clock will initiate
the flag update cycle.
When updating the flags, the CY7C441/443 decide whether or
not the opposite clock was recognized when a clock updates
the flag. For example, if a write occurs at least tSKEW1 after a
read when updating the Empty flag, the write is guaranteed not
to be included when CKR updates the flag. If a write occurs at
least tSKEW2 before a read, the write is guaranteed to be in-
cluded when CKR updates the flag. If a write occurs within
tSKEW1/tSKEW2 after or before CKR, then the decision of
Document #: 38-06032 Rev. *A
Page 10 of 15
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